2024-01-19 11:32:57 -08:00
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/*
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* Copyright © 2015-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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2024-01-19 15:24:34 -08:00
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#include "elk_compiler.h"
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#include "elk_shader.h"
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#include "elk_eu.h"
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#include "elk_nir.h"
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2024-02-14 15:49:45 -08:00
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#include "elk_nir_options.h"
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2024-01-19 11:32:57 -08:00
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#include "dev/intel_debug.h"
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#include "compiler/nir/nir.h"
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#include "util/u_debug.h"
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2024-01-19 18:46:03 -08:00
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struct elk_compiler *
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elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
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{
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assert(devinfo->ver <= 8);
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struct elk_compiler *compiler = rzalloc(mem_ctx, struct elk_compiler);
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compiler->devinfo = devinfo;
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2024-01-19 18:46:03 -08:00
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elk_init_isa_info(&compiler->isa, devinfo);
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2024-01-19 18:46:03 -08:00
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elk_fs_alloc_reg_sets(compiler);
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2024-01-19 11:32:57 -08:00
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if (devinfo->ver < 8)
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elk_vec4_alloc_reg_set(compiler);
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compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false);
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/* Default to the sampler since that's what we've done since forever */
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compiler->indirect_ubos_use_sampler = true;
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/* There is no vec4 mode on Gfx10+, and we don't use it at all on Gfx8+. */
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for (int i = MESA_SHADER_VERTEX; i < MESA_ALL_SHADER_STAGES; i++) {
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compiler->scalar_stage[i] = devinfo->ver >= 8 ||
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i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE;
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}
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nir_lower_int64_options int64_options =
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nir_lower_imul64 |
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nir_lower_isign64 |
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nir_lower_divmod64 |
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nir_lower_imul_high64 |
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nir_lower_find_lsb64 |
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nir_lower_ufind_msb64 |
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nir_lower_bit_count64;
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nir_lower_doubles_options fp64_options =
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nir_lower_drcp |
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nir_lower_dsqrt |
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nir_lower_drsq |
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nir_lower_dsign |
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nir_lower_dtrunc |
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nir_lower_dfloor |
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nir_lower_dceil |
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nir_lower_dfract |
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nir_lower_dround_even |
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nir_lower_dmod |
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nir_lower_dsub |
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nir_lower_ddiv;
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if (!devinfo->has_64bit_float || INTEL_DEBUG(DEBUG_SOFT64))
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fp64_options |= nir_lower_fp64_full_software;
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if (!devinfo->has_64bit_int)
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int64_options |= (nir_lower_int64_options)~0;
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/* The Bspec's section titled "Instruction_multiply[DevBDW+]" claims that
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* destination type can be Quadword and source type Doubleword for Gfx8 and
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* Gfx9. So, lower 64 bit multiply instruction on rest of the platforms.
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*/
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2024-02-13 13:20:08 -08:00
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if (devinfo->ver < 8)
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int64_options |= nir_lower_imul_2x32_64;
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/* We want the GLSL compiler to emit code that uses condition codes */
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for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
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struct nir_shader_compiler_options *nir_options =
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rzalloc(compiler, struct nir_shader_compiler_options);
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bool is_scalar = compiler->scalar_stage[i];
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if (is_scalar) {
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*nir_options = elk_scalar_nir_options;
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int64_options |= nir_lower_usub_sat64;
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} else {
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*nir_options = elk_vector_nir_options;
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}
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/* Prior to Gfx6, there are no three source operations, and Gfx11 loses
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* LRP.
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*/
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nir_options->lower_ffma16 = devinfo->ver < 6;
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nir_options->lower_ffma32 = devinfo->ver < 6;
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nir_options->lower_ffma64 = devinfo->ver < 6;
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nir_options->lower_flrp32 = devinfo->ver < 6;
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nir_options->has_bfe = devinfo->ver >= 7;
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nir_options->has_bfm = devinfo->ver >= 7;
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nir_options->has_bfi = devinfo->ver >= 7;
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nir_options->lower_bitfield_reverse = devinfo->ver < 7;
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nir_options->lower_find_lsb = devinfo->ver < 7;
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nir_options->lower_ifind_msb = devinfo->ver < 7;
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nir_options->lower_int64_options = int64_options;
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nir_options->lower_doubles_options = fp64_options;
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nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
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2024-11-29 17:43:34 -05:00
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nir_options->support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
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nir_options->support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
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nir_options->force_indirect_unrolling |=
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elk_nir_no_indirect_mask(compiler, i);
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nir_options->force_indirect_unrolling_sampler = devinfo->ver < 7;
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2024-02-13 13:20:08 -08:00
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nir_options->divergence_analysis_options |=
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nir_divergence_single_prim_per_subgroup;
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compiler->nir_options[i] = nir_options;
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}
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return compiler;
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}
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static void
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insert_u64_bit(uint64_t *val, bool add)
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{
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*val = (*val << 1) | !!add;
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}
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uint64_t
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elk_get_compiler_config_value(const struct elk_compiler *compiler)
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{
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uint64_t config = 0;
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unsigned bits = 0;
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insert_u64_bit(&config, compiler->precise_trig);
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bits++;
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uint64_t mask = DEBUG_DISK_CACHE_MASK;
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bits += util_bitcount64(mask);
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u_foreach_bit64(bit, mask)
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insert_u64_bit(&config, INTEL_DEBUG(1ULL << bit));
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mask = SIMD_DISK_CACHE_MASK;
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bits += util_bitcount64(mask);
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u_foreach_bit64(bit, mask)
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insert_u64_bit(&config, (intel_simd & (1ULL << bit)) != 0);
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mask = 3;
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bits += util_bitcount64(mask);
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assert(bits <= util_bitcount64(UINT64_MAX));
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return config;
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}
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unsigned
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elk_prog_data_size(gl_shader_stage stage)
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{
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static const size_t stage_sizes[] = {
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[MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_data),
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[MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_data),
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[MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_data),
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[MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_data),
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[MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_data),
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[MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_data),
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};
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assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
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return stage_sizes[stage];
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}
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unsigned
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elk_prog_key_size(gl_shader_stage stage)
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{
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static const size_t stage_sizes[] = {
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[MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_key),
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[MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_key),
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[MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_key),
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[MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_key),
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[MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_key),
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[MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_key),
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};
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assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
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return stage_sizes[stage];
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}
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void
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elk_write_shader_relocs(const struct elk_isa_info *isa,
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void *program,
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const struct elk_stage_prog_data *prog_data,
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struct elk_shader_reloc_value *values,
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unsigned num_values)
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{
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for (unsigned i = 0; i < prog_data->num_relocs; i++) {
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assert(prog_data->relocs[i].offset % 8 == 0);
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void *dst = program + prog_data->relocs[i].offset;
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for (unsigned j = 0; j < num_values; j++) {
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if (prog_data->relocs[i].id == values[j].id) {
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uint32_t value = values[j].value + prog_data->relocs[i].delta;
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switch (prog_data->relocs[i].type) {
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case ELK_SHADER_RELOC_TYPE_U32:
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*(uint32_t *)dst = value;
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break;
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case ELK_SHADER_RELOC_TYPE_MOV_IMM:
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elk_update_reloc_imm(isa, dst, value);
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break;
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default:
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unreachable("Invalid relocation type");
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}
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break;
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}
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}
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}
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}
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