Ben Skeggs
5bd0e52dba
nouveau: ack PFIFO interrupts at PFIFO, not PMC.
2007-03-07 21:00:55 +11:00
Thomas Hellstrom
6ffe94f008
Add via CX700.
2007-03-07 09:19:57 +01:00
Dave Airlie
188a93c9df
radeon: make PCI GART aperture size variable, but making table size variable
...
This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
Dave Airlie
c9178c3d01
ati: make pcigart code able to handle variable size PCI GART aperture
...
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
Ben Skeggs
72caa48c82
nouveau: intrusive drm interface changes
...
graphics objects:
- No longer takes flags/dmaobj parameters, requires some major changes
to the ddx to setup the object through the FIFO. This change is
likely to cause breakages on some cards (tested on NV05,NV28,NV35,
NV40 and NV4E).
dma objects:
- now takes a "class" parameter, not really used yet but we may need
it at some point.
- parameters are checked, so clients can't randomly create DMA objects
pointing at whatever they feel like.
misc:
- Added FB_SIZE/AGP_SIZE getparams
- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
Jakob Bornecrantz
9d8ba2d0d4
drm: remove unnecessary NULL checks, and fix some indents..
2007-02-25 10:48:26 +11:00
Thomas Hellstrom
e0f53e59be
Simple fence object sample driver for via, based on idling the GPU.
...
Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
2007-02-16 20:22:24 +01:00
Thomas Hellstrom
7766378d97
Initial support for fence object classes.
...
(Fence objects belonging to different command submission mechanisms).
2007-02-15 12:11:38 +01:00
Thomas Hellstrom
a78f70faad
Merge branch 'ttm-vram-0-1-branch'
2007-02-14 15:33:40 +01:00
Thomas Hellstrom
5c9a7b0f94
Remove an intel-specific hack and replace it with a fence driver callback.
2007-02-14 13:31:35 +01:00
Stephane Marchesin
f524870184
nouveau: fix the build on big endian (thanks CyberFoxx)
2007-02-14 00:08:55 +01:00
B. Rathmann
59af900e4f
nouveau: fix memory initialization with multiple cards.
2007-02-14 00:07:31 +01:00
Thomas Hellstrom
e1460426b8
Bugzilla Bug #9457
...
Add refcounting of user waiters to the DRM hardware lock, so that we can use the
DRM_LOCK_CONT flag more conservatively.
Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context,
when it is released. This is useful when waiting for idle and can be used
for very simple fence object driver implementations for the new memory manager.
It also resolves the AIGLX startup deadlock for the sis and the via drivers.
i810, i830 still require that the hardware lock is really taken so the deadlock remains
for those two. I'm not sure about ffb. Anyone familiar with that code?
2007-02-13 20:47:30 +01:00
Thomas Hellstrom
abc14ddfb5
Update flags and comments.
2007-02-12 21:40:42 +01:00
Thomas Hellstrom
53aee3122a
I915 accelerated blit copy functional.
...
Fixed - to System memory copies are implemented by
flipping in a cache-coherent TTM,
blitting to it, and then flipping it out.
2007-02-09 16:36:53 +01:00
Eric Anholt
898aca1a66
Warning fix: correct type of i915_mmio argument.
2007-02-07 21:26:02 -08:00
Eric Anholt
ef9a9d3cd1
Define __iomem for systems without it.
2007-02-07 21:26:01 -08:00
Eric Anholt
8918748058
Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list.
2007-02-07 21:26:01 -08:00
Thomas Hellstrom
c1fbd8a566
Checkpoint commit.
...
Flag handling and memory type selection cleanup.
glxgears won't start.
2007-02-07 17:25:13 +01:00
Thomas Hellstrom
609e3b0375
Implement a policy for selecting memory types.
2007-02-06 14:20:33 +01:00
Stephane Marchesin
17985f07d6
nouveau: more work on the nv04 context switch code.
2007-02-06 01:17:32 +01:00
Stephane Marchesin
8c663b4e56
nouveau: and of course, I was missing the last nv04 piece.
2007-02-03 06:13:27 +01:00
Stephane Marchesin
0c13657c33
nouveau: plugin the nv04 graph init function.
2007-02-03 06:00:29 +01:00
Stephane Marchesin
7ab9e7f36f
nouveau: cleanup the nv04 pgraph save/restore mechanism.
2007-02-03 05:56:42 +01:00
Stephane Marchesin
d69902db3b
nouveau: fix nv04 graph routines for new register names.
2007-02-03 05:25:36 +01:00
Stephane Marchesin
5a072f32c8
nouveau: rename registers to their proper names.
2007-02-03 04:57:06 +01:00
Stephane Marchesin
e64dbef911
nouveau: add NV04 registers required for PGRAPH context switching.
2007-02-03 04:23:09 +01:00
Matthieu Castet
55f7859a25
nouveau: nv ctx switch opps the size of array was wrong
2007-02-02 23:01:03 +01:00
Matthieu Castet
63cf3b3da7
nouveau: nv10 ctx switch, some regs are nv17+ only
2007-02-02 20:08:33 +01:00
Thomas Hellstrom
6c04185857
via: Try to improve command-buffer chaining.
...
Bump driver date and patchlevel.
2007-02-02 09:22:30 +01:00
Thomas Hellstrom
70bba11bc7
Disable AGP DMA for chips with the new 3D engine.
2007-02-02 09:22:15 +01:00
Thomas Hellstrom
3024f23c65
memory manager: Make device driver aware of different memory types.
...
Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:
1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.
In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.
This also makes support for unmappable VRAM simple to implement.
2007-01-31 14:50:57 +01:00
Ben Skeggs
ee4ac5c897
nouveau: determine chipset type at startup, instead of every time we use it.
2007-01-28 23:48:33 +11:00
Matthieu Castet
c744bfde2d
make works ctx switch on nv10.
2007-01-26 21:57:44 +01:00
Patrice Mandin
9c03ca81e7
nouveau: oops, wrong indexing in nv17 regs
2007-01-26 21:05:59 +01:00
Patrice Mandin
5534c90ff3
nouveau: read gpu type once
2007-01-26 19:54:35 +01:00
Patrice Mandin
05d3ed472e
nouveau: only save/restore nv17 regs on nv17,18 hw
2007-01-26 19:25:49 +01:00
Patrice Mandin
e7ba15a003
nouveau: add extra pgraph registers
2007-01-26 19:24:34 +01:00
Patrice Mandin
d4c9f135b5
nouveau: add some nv10 pgraph defines
2007-01-26 18:10:31 +01:00
Patrice Mandin
6d9ef1a960
nouveau: simplify and fix BIG_ENDIAN flags
2007-01-25 23:06:48 +01:00
Ben Skeggs
90ae39d2f0
nouveau: nv4c default context
2007-01-25 11:11:01 +11:00
Ben Skeggs
aa7266385e
nouveau: always print nsource/nstatus regs on PGRAPH errors
2007-01-25 08:16:23 +11:00
Zou Nan hai
7d4e6b1445
vblank interrupt fix
2007-01-24 16:33:21 +08:00
Ben Skeggs
19ba074938
nouveau: fix getparam from 32-bit client on 64-bit kernel
2007-01-19 15:41:51 +11:00
Ben Skeggs
4291df69bd
nouveau: re-add 6150 Go pciid (0x0244)
2007-01-19 15:16:18 +11:00
Jeremy Kolb
a40de938fa
nouveau: cleanup nv30_graph.c
2007-01-18 21:40:21 -05:00
Jeremy Kolb
ab72a7714e
nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.
2007-01-18 21:40:21 -05:00
Dave Jones
bd0418cb01
add missing quadro id
2007-01-18 17:35:28 +11:00
Jeremy Kolb
78a4f5c1bc
nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
...
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.
Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
Matthieu Castet
fdbc34fab0
nouveau: opps nv20 ctx ramin size was wrong
2007-01-14 20:04:20 +01:00
