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1788 commits

Author SHA1 Message Date
Dave Airlie
36e11dd380 r500: fragment program upload is also used to upload constants. 
Limit frag address to 8 bits
 2008-03-21 16:59:52 +10:00
Jerome Glisse
71b66b0043 Merge branch 'modesetting-101' of ssh://git.freedesktop.org/git/mesa/drm into modesetting-101 2008-03-20 17:44:32 +01:00
Jerome Glisse
6ef119abf5 radeon_ms: fix fence 2008-03-20 17:43:43 +01:00
Dave Airlie
316979356f drm: fixup r500fp submission 2008-03-20 14:20:53 +10:00
Stuart Bennett
1021799b6c nouveau: do not set on-board timer's numerator/denominator to bad values 2008-03-20 02:57:58 +00:00
Alex Deucher
9e4f908287 RADEON: switch over to new production microcode 
This needs to be tested thoroughly before pushing to the
kernel.
 2008-03-19 15:37:56 -04:00
Alex Deucher
d8af16d2a7 RADEON: production microcode for all radeons, r1xx-r6xx 
This updated microcode is not in use yet.
 2008-03-19 14:57:42 -04:00
Dave Airlie
a3c808d8fe move some more r300 regs into not allowed on r500 2008-03-19 16:10:37 +10:00
Dave Airlie
d18c2c6842 drm: add new rs690 pci id 2008-03-18 09:07:45 +10:00
Dave Airlie
607964ed9e drm: add master set/drop protocol 
this may not survive long - just need something for testing
 2008-03-17 16:38:20 +10:00
Dave Airlie
2d0411cb75 i915: safety check the sarea map still exists 2008-03-17 16:38:18 +10:00
Dave Airlie
3add949403 initial r500 RS and FP register and upload code 2008-03-17 11:08:03 +10:00
Dave Airlie
1f96e9a982 drm/pcigart: fix the pci gart to use the drm_pci wrapper. 
This is the correct fix for the RS690 and hopefully the dma coherent work.

For now we limit everybody to a 32-bit DMA mask but it is possible for
RS690 to use a 40-bit DMA mask for the GART table itself,
and the PCIE cards can use 40-bits for the table entries.

Signed-off-by: Dave Airlie <airlied@redhat.com>
 2008-03-17 07:05:46 +10:00
Thomas Hellstrom
1a2d8c4bfa Avoid unnecessary waits for command regulator pause. 2008-03-16 20:07:14 +01:00
Thomas Hellstrom
3a3a9485aa [via] Remove some leftover vars. 2008-03-16 11:45:58 +01:00
Thomas Hellstrom
7d3d15e67d [via] The millionth fixup for the millionth-1 attempt to stabilize the AGP 
DMA command submission. It's worth remembering that all new bright ideas on how
to make this command reader work properly and according to docs
will probably fail :( Bring in some old code.
 2008-03-16 11:45:57 +01:00
Thomas Hellstrom
563fe9dcd4 [via] Fix driver after vblank-rework merge. 2008-03-16 11:45:57 +01:00
Dave Airlie
5b1d9263d3 drm/rs690: set AGP_BASE_2 to 0 2008-03-16 14:00:16 +10:00
Dave Airlie
dd9eb923ed drm: set rs690 gart base completly. 
The docs state bits 4-11 represent bits 32-39 of a 40-bit address
 2008-03-16 12:58:07 +10:00
Alex Deucher
9be916f353 Fix chip family for RV550 2008-03-12 11:16:12 -04:00
Ben Skeggs
1766e1c07b nv50: force channel vram access through vm 
If we ever want to be able to use the 3D engine we have no choice.  It
appears that the tiling setup (required for 3D on G8x) is in the page tables.

The immediate benefit of this change however is that it's now not possible
for a client to use the GPU to render over the top of important engine setup
tables, which also live in VRAM.

G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping
of real vram pages to their offset within the start of a channel's VRAM
DMA object and only populate a single PDE for VRAM use.
 2008-03-13 00:23:52 +11:00
Thomas Hellstrom
88bd1e4a35 Merge branch 'intel-post-reloc' 
Conflicts:

	linux-core/drm_compat.c
	linux-core/drm_compat.h
	linux-core/drm_ttm.c
	shared-core/i915_dma.c

Bump driver minor to 13 due to introduction of new
relocation type.
 2008-03-12 11:34:29 +01:00
Alan Hourihane
b6dc381fab Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into modesetting-101 
Conflicts:

	shared-core/i915_dma.c
	shared-core/i915_drv.h
	shared-core/i915_irq.c
 2008-03-12 10:18:33 +00:00
Thomas Hellstrom
8a18d123f5 Avoid large kmallocs. 2008-03-12 09:49:27 +01:00
Alan Hourihane
cf1a2499ed global hotplug events happen in the pipe A stat register, 
they are not pipe A specific. Remove pipe B code.
 2008-03-11 21:24:29 +00:00
Alan Hourihane
903d9231d6 Add support for monitor hotplug signals/waits 
Also adjust i915 irq handling as it follows the 16bit'ism's
of the i8xx series.
 2008-03-11 20:30:25 +00:00
Stuart Bennett
f13936f7fc nouveau: move AGP reset to mem_init_agp 
Also, power cycle PGRAPH when resetting AGP -- it seems to fix problems encountered by p0g on nv25
 2008-03-11 16:45:35 +00:00
Dave Airlie
5a7f4b3074 drm: fix oops on unload. 
if we are unloading the module, there is no master so therefore no lock
 2008-03-11 16:05:26 +10:00
Dave Airlie
52748d1792 drm: hopefully fix cursors on 965 2008-03-11 13:23:33 +10:00
Jerome Glisse
a7e6ca62ad Merge branch 'modesetting-101' of ssh://git.freedesktop.org/git/mesa/drm into modesetting-101 2008-03-10 23:36:27 +01:00
Jerome Glisse
a7dc4d08b9 rradeon_ms: rework fence code and bring radeon ms up to date 2008-03-10 23:35:07 +01:00
Keith Packard
2848f04861 Switch from PIPE_VBLANK to PIPE_EVENT interrupts. 
My 965GM gets interrupts stuck when using the old PIPE_VBLANK interrupt.
Switch to the PIPE_EVENT interrupt mechanism, and set the PIPE*STAT
registers to use START_VBLANK on 965 and VBLANK on previous chips.
 2008-03-08 00:04:30 -08:00
Dave Airlie
ce3733572e drm/radeon: check sarea_priv exists 2008-03-08 08:30:30 +10:00
Ben Skeggs
1ccccbd4ce nouveau: redo channel idle detection 
Will hopefully work a bit better than previous code, which depended on
knowing the channel's most recent PUT value.  Some chips always return
0 on reading these regs, and currently userspace is the only other entity
which knows the value.
 2008-03-07 15:18:34 +11:00
Ben Skeggs
cd924de029 nouveau: don't touch NV_USER regs on channel destroy. 
Not only was this entirely pointless, it actually causes my NV30GL to
die randomly when channels are destroyed.
 2008-03-07 15:18:34 +11:00
Dave Airlie
cf28ca4212 actually turn the irq off 2008-03-07 13:03:32 +11:00
Dave Airlie
ccae12a837 I really screwed up that merge somehow 2008-03-07 08:58:24 +10:00
Dave Airlie
48a166af14 woah somehow got these upstream 2008-03-07 08:49:27 +10:00
Dave Airlie
44a2209790 Merge branch 'master' of ../../drm into modesetting-101 
Conflicts:

	shared-core/drm.h
 2008-03-06 05:39:07 +10:00
Dave Airlie
d5c0101252 ttm: make sure userspace can't destroy kernel create memory managers 
this adds something to say the kernel initialised the memory region not
the userspace. and blocks userspace from deallocating kernel areas
 2008-03-06 05:37:54 +10:00
Dave Airlie
180c9188f4 drm/ttm: add ioctl to get back memory managed area sized 
taken from modesetting branch but could be useful outside it.
 2008-03-06 05:31:50 +10:00
Dave Airlie
e00dea812d Merge branch 'master' of ../../drm into modesetting-101 
Conflicts:

	linux-core/drmP.h
	linux-core/drm_drv.c
	linux-core/drm_proc.c
	linux-core/drm_stub.c
	linux-core/drm_sysfs.c
 2008-03-06 05:26:23 +10:00
Dave Airlie
12574590cd drm: reorganise minor number handling using code from modesetting branch 
Rip out the whole head thing and replace it with an idr and drm_minor
structure.
 2008-03-06 05:21:50 +10:00
Xiang, Haihao
638353103d i915: Evict if relocatee buffer is CACHED_MAPPED before 
writting relocations, otherwise the GPU probably sees some
inconsistent data. Fix fd.o bug#14656
 2008-03-05 15:09:17 +08:00
Dave Airlie
4dbf447f43 drm: fixup compat with old x.org drivers 2008-03-05 15:28:38 +10:00
Dave Airlie
43891ff2d0 Merge remote branch 'origin/master' into modesetting-101 
Conflicts:

	linux-core/drm_compat.c
 2008-03-05 10:37:02 +10:00
Eric Anholt
a6a2f2c8c4 Clarify when WAIT_LAZY is relevant to users. 2008-03-04 13:45:41 -08:00
Eric Anholt
3332a0add6 Remove unused DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS. 2008-03-04 13:41:30 -08:00
Zou Nan hai
63fd6f284d [i915] 2D driver may reset Frame count value, this may lead driver 
to leap it's vblank count a huge value.
  This will stall some applications that switch video mode if vblank_mode is set to a non zero value in drirc.
 2008-03-03 14:49:49 +08:00
Alan Hourihane
9c5ba9f5d1 Add FENCE registers to MMIO list 2008-03-02 21:48:40 +00:00