Ben Skeggs
ec67c2def9
nouveau: G8x PCIEGART
...
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART
support for G8X using the current mm has been hacked on top of it.
2007-07-17 13:51:14 +10:00
Ian Romanick
70a8a60a3e
Correct errors in the usage of pci_map_page.
...
With these changes the driver no longer instantly hard-locks a 6600LE
on a PowerPC G5. I haven't tested any 3D apps yet.
2007-07-16 10:56:43 -07:00
Eric Anholt
3f04fe7890
Fix FreeBSD build.
2007-07-16 01:53:06 -07:00
Dave Airlie
24311d5d82
drm: remove drm_buf_t
2007-07-16 13:42:11 +10:00
Dave Airlie
be85ad0333
drm: detypedef ttm/bo/fence code
2007-07-16 13:37:02 +10:00
Dave Airlie
6dce9e0735
drm: remove hashtab/sman and object typedefs
2007-07-16 12:48:44 +10:00
Dave Airlie
21ee6fbfb8
drm: remove drmP.h internal typedefs
2007-07-16 12:32:51 +10:00
Dave Airlie
1a07256d60
drm: remove ttm userspace typedefs
2007-07-16 11:30:53 +10:00
Dave Airlie
b95ac8b7b3
drm: detypedef drm.h and fixup all problems
2007-07-16 11:22:15 +10:00
Dave Airlie
f174f835ff
drm: remove typedefs in drm.h to their own section
2007-07-16 10:13:58 +10:00
Dave Airlie
2134193af6
Merge branch 'drm-ttm-cleanup-branch'
2007-07-16 10:05:20 +10:00
Patrice Mandin
bc7d6c76fa
nouveau: nv10 and nv11/15 are different
2007-07-14 18:32:11 +02:00
Arthur Huillet
aa6d9199fa
applied patch from Ian Romanick fixing PCI DMA object creation code
2007-07-13 20:51:52 +02:00
Arthur Huillet
5ae3ad4f01
now attempting to create PCI object only when there is a pci_heap
2007-07-13 16:00:03 +02:00
Ben Skeggs
0029713451
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-13 15:09:31 +10:00
Ian Romanick
5522136b7f
Merge branch 'master' into xgi-0-0-2
2007-07-12 15:28:17 -07:00
Ben Skeggs
851c950d98
nouveau: unbreak AGP
2007-07-13 02:18:59 +10:00
Ben Skeggs
af317f1cc7
nouveau: mem_alloc() returns offsets, not absolute addresses now.
2007-07-12 11:55:47 +10:00
Ben Skeggs
522a0c868c
nouveau: nuke left over debug message
2007-07-12 11:39:45 +10:00
Ben Skeggs
750371cb6e
nouveau: separate region_offset into map_handle and offset.
2007-07-12 10:46:57 +10:00
Arthur Huillet
5fbdf9da8b
fixed object creation code to not Oops on 64bits, worked around memalloc not working on 64bit for PCIGART
2007-07-12 02:35:39 +02:00
Arthur Huillet
b301a9051b
NV50 will not attempt to use PCIGART now
2007-07-11 15:01:37 +02:00
Arthur Huillet
d26ae22c2b
fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will probably still have a problem
2007-07-11 14:56:27 +02:00
Ben Skeggs
5ccadac9e3
nouveau/nv50: G80 fixes.
...
Again, no hardware, so no idea if it'll even work yet. I understand how
the PRAMIN setup works now, un-hardcoding stuff will come "RealSoonNow(tm)".
2007-07-11 14:22:59 +10:00
Ben Skeggs
13e1377044
nouveau: Some checks on userspace object handles.
2007-07-11 12:39:30 +10:00
Dave Airlie
2c9e05cf4c
Merge branch 'master' into cleanup
...
Conflicts:
libdrm/xf86drm.c
linux-core/drm_bo.c
linux-core/drm_fence.c
2007-07-11 11:23:41 +10:00
Arthur Huillet
694e1c5c3f
Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.
2007-07-11 02:35:10 +02:00
Ian Romanick
a9c49be6f8
Fix ioctl types.
...
I had moved code from xgi_drv.h to xgi_drm.h before changing the ioctl
types for XGI_IOCTL_(FB|PCIE)_ALLOC.
2007-07-09 18:52:43 -07:00
Ian Romanick
1f4e24b429
Move types shared with user mode to xgi_drm.h.
2007-07-09 16:33:14 -07:00
Ben Skeggs
023f7d9c00
nouveau: Allocate mappable VRAM for notifiers..
2007-07-09 23:58:00 +10:00
Ben Skeggs
31e33813e8
nouveau: Don't be so strict on <NV50
2007-07-09 20:02:14 +10:00
Ben Skeggs
3c58195ccd
nouveau: Avoid oops
...
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09 16:16:44 +10:00
Ben Skeggs
c806bba466
nouveau/nv50: Initial channel/object support
...
Should be OK on G84 for a single channel, multiple channels *almost* work.
Untested on G80.
2007-07-09 16:16:44 +10:00
Ben Skeggs
3324342e42
nouveau: enable reporting for all PFIFO/PGRAPH irqs
2007-07-09 16:16:44 +10:00
Ben Skeggs
163f852612
nouveau: rewrite gpu object code
...
Allows multiple references to a single object, needed to support PCI(E)GART
scatter-gather DMA objects which would quickly fill PRAMIN if each channel
had its own.
Handle per-channel private instmem areas. This is needed to support NV50,
but might be something we want to do on earlier chipsets at some point?
Everything that touches PRAMIN is a GPU object.
2007-07-09 16:16:44 +10:00
Michel Dänzer
91990946fa
One more spinlock initializer cleanup.
2007-07-03 12:33:51 +02:00
Ben Skeggs
e26ec51146
nouveau: small RAMFC cleanups
2007-06-29 14:20:50 +10:00
Ben Skeggs
1c32fecd6d
nouveau: Hack around possible Xv blit adaptor breakage
2007-06-28 21:01:17 +10:00
Ben Skeggs
2dd85772aa
nouveau/nv10: Fix earlier NV1x chips
...
Can't use nv04 code for them, since an extra field was inserted into
RAMFC after DMA_PUT/GET.
2007-06-28 04:23:17 +10:00
Ben Skeggs
68ecf61647
nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit
2007-06-28 03:26:44 +10:00
Ben Skeggs
18a6d1c9c3
nouveau: simplify PRAMIN access
2007-06-28 03:26:44 +10:00
Ben Skeggs
38617b6a26
nouveau: name some regs
2007-06-28 03:26:44 +10:00
Ben Skeggs
ce0d528d3c
nouveau/nv50: skeletal backend
2007-06-28 03:26:43 +10:00
Ben Skeggs
695599f18d
nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)
...
For various reasons, this ioctl was a bad idea.
At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.
However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers). Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28 03:26:43 +10:00
Ben Skeggs
4f2dd78ff3
nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks
2007-06-28 03:04:48 +10:00
Thomas Hellstrom
9b9a127ed0
More 64-bit padding.
2007-06-26 23:25:40 +02:00
Ian Romanick
5c27f8a70e
Add support SiS based XGI chips to SiS DRM.
2007-06-26 09:51:55 -07:00
Ben Skeggs
9f617522d9
nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303
2007-06-25 01:57:57 +10:00
Ben Skeggs
3dfc13e2da
nouveau: kill some dead code
2007-06-24 19:00:44 +10:00
Ben Skeggs
5f05cd7086
nouveau: NV04/NV10/NV20 PGRAPH engtab functions
...
NV04/NV10 load_context()/save_context() are stubs. I don't know enough about
how they work to implement them sanely. The "old" context_switch() code
remains hooked up, so it shouldn't break anything.
NV20 will probably break if load_context() works. No inital context values
are filled in, so when the first channel is created PGRAPH will probably end
up having its state zeroed. Some setup from nv20_graph_init() will probably
need to be moved to the per-channel context setup.
2007-06-24 19:00:26 +10:00
