It seems fbcon_sync will get called continually by something even while
not at a console, so ignore the call unless we've previously rendered
to the fbcon.
This is a essentially a big squash merge from the kernel tree I've been
working in, sorry about the loss of history, but commiting each patch
individually would've taken quite a while to do.
The nv50 kms code now uses the helpers in the drm, simplifying the
code greatly.
The code is far more stable than previously on all the G8x cards I've
been able to test on, but there's likely still bugs to be ironed out!
Not really necessary it seems as we've been dealing without it for a while
now. But, it's useful to be sure that we don't end up with stale bits
of state laying around.
NV04 was completely busted. Push buffers were getting allocated at the
end of VRAM, overwriting PRAMIN. So, it turns out PRAMIN is in VRAM on
all chips. Question answered!
Several nvidia-based systems don't support backlight control via the
standard ACPI control mechanisms. Instead, it's necessary for the driver
to modify the backlight control registers directly. This patch adds
support for determining whether the registers appear to be in use, and
if so registers a kernel backlight device to control them. The backlight
can then be controlled via existing userspace tools.
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This patch tries to use the available fence count to figure out whether a
given batch can succeed or not (just like the aperture check).
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 2fa5f28eee)
NVIDIA do this fun little sequence after updating the PRAMIN page tables.
On 9xxx chips, none of the PRAMIN BAR bindings (except the initial one)
worked, hence the majority of the setup needed to create a channel
ended up in the wrong place, causing all sorts of fun.
This is done by NVIDIA on nv8x chips also, so we'll do it for them too,
even though they appear to work without it.
I'm not 100% sure that the nv94 one we were using won't work. The context
layouts are identical (well.. same ctxprog, so of course!), only a couple
of registers differ. But, be safe until we actually get some 9xxx chips
working.
Our PFIFO/PGRAPH context save/load functions don't really work well
(at all?) on nv5x yet. Depending on what random state the card is
in before the drm loads, fbcon probably won't work correctly.
Luckily we've setup the GPU in such a way that it'll actually do a
hw context switch for the first context. Not sure of how successful
this'd be currently on the older chips (actually, pretty sure it won't
work), so NV50 only for now.
