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radeon: fixup for kms api

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This commit is contained in:
Dave Airlie 2009-04-06 09:53:22 +10:00
parent 7677fd4765
commit 96982ffc09
6 changed files with 80 additions and 232 deletions
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6
libdrm/radeon/radeon_bo_gem.c
View file

@ -94,7 +94,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
args.size = size;
args.alignment = alignment;
args.initial_domain = bo->base.domains;
args.no_backing_store = 0;
args.flags = 0;
args.handle = 0;
r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE,
&args, sizeof(args));
@ -179,12 +179,12 @@ static int bo_unmap(struct radeon_bo *bo)
static int bo_wait(struct radeon_bo *bo)
{
struct drm_radeon_gem_wait_rendering args;
struct drm_radeon_gem_wait_idle args;
int ret;
args.handle = bo->handle;
do {
ret = drmCommandWriteRead(bo->bom->fd, DRM_RADEON_GEM_WAIT_RENDERING,
ret = drmCommandWriteRead(bo->bom->fd, DRM_RADEON_GEM_WAIT_IDLE,
&args, sizeof(args));
} while (ret == -EAGAIN);
return ret;

127
linux-core/radeon_gem.c
View file

@ -63,11 +63,9 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
struct drm_radeon_private *dev_priv = dev->dev_private;
struct drm_radeon_gem_info *args = data;
args->vram_start = dev_priv->mm.vram_offset;
args->vram_size = dev_priv->mm.vram_size;
args->vram_visible = dev_priv->mm.vram_visible;
args->gart_start = dev_priv->mm.gart_start;
args->gart_size = dev_priv->mm.gart_useable;
return 0;
@ -131,7 +129,7 @@ int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
/* create a gem object to contain this object in */
args->size = roundup(args->size, PAGE_SIZE);
obj = radeon_gem_object_alloc(dev, args->size, args->alignment, args->initial_domain, args->no_backing_store);
obj = radeon_gem_object_alloc(dev, args->size, args->alignment, args->initial_domain, args->flags & RADEON_GEM_NO_BACKING_STORE);
if (!obj)
return -EINVAL;
@ -340,86 +338,16 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
}
int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
struct drm_radeon_gem_pin *args = data;
struct drm_gem_object *obj;
struct drm_radeon_gem_object *obj_priv;
int ret;
int flags = DRM_BO_FLAG_NO_EVICT;
int mask = DRM_BO_FLAG_NO_EVICT;
/* check for valid args */
if (args->pin_domain) {
mask |= DRM_BO_MASK_MEM;
if (args->pin_domain == RADEON_GEM_DOMAIN_GTT)
flags |= DRM_BO_FLAG_MEM_TT;
else if (args->pin_domain == RADEON_GEM_DOMAIN_VRAM)
flags |= DRM_BO_FLAG_MEM_VRAM;
else /* hand back the offset we currently have if no args supplied
- this is to allow old mesa to work - its a hack */
flags = 0;
}
obj = drm_gem_object_lookup(dev, file_priv, args->handle);
if (obj == NULL)
return -EINVAL;
obj_priv = obj->driver_private;
/* validate into a pin with no fence */
DRM_DEBUG("got here %p %p %d\n", obj, obj_priv->bo, atomic_read(&obj_priv->bo->usage));
if (flags && !(obj_priv->bo->type != drm_bo_type_kernel && !DRM_SUSER(DRM_CURPROC))) {
ret = drm_bo_do_validate(obj_priv->bo, flags, mask,
DRM_BO_HINT_DONT_FENCE, 0);
} else
ret = 0;
args->offset = obj_priv->bo->offset;
DRM_DEBUG("got here %p %p %x\n", obj, obj_priv->bo, obj_priv->bo->offset);
mutex_lock(&dev->struct_mutex);
drm_gem_object_unreference(obj);
mutex_unlock(&dev->struct_mutex);
return ret;
}
int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
struct drm_radeon_gem_unpin *args = data;
struct drm_gem_object *obj;
struct drm_radeon_gem_object *obj_priv;
int ret;
obj = drm_gem_object_lookup(dev, file_priv, args->handle);
if (obj == NULL)
return -EINVAL;
obj_priv = obj->driver_private;
/* validate into a pin with no fence */
ret = drm_bo_do_validate(obj_priv->bo, 0, DRM_BO_FLAG_NO_EVICT,
DRM_BO_HINT_DONT_FENCE, 0);
mutex_lock(&dev->struct_mutex);
drm_gem_object_unreference(obj);
mutex_unlock(&dev->struct_mutex);
return ret;
}
int radeon_gem_busy(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
return 0;
}
int radeon_gem_wait_rendering(struct drm_device *dev, void *data,
struct drm_file *file_priv)
int radeon_gem_wait_idle(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
struct drm_radeon_gem_wait_rendering *args = data;
struct drm_radeon_gem_wait_idle *args = data;
struct drm_gem_object *obj;
struct drm_radeon_gem_object *obj_priv;
int ret;
@ -1559,50 +1487,3 @@ static void radeon_gem_dma_bufs_destroy(struct drm_device *dev)
}
}
static struct drm_gem_object *gem_object_get(struct drm_device *dev, uint32_t name)
{
struct drm_gem_object *obj;
spin_lock(&dev->object_name_lock);
obj = idr_find(&dev->object_name_idr, name);
if (obj)
drm_gem_object_reference(obj);
spin_unlock(&dev->object_name_lock);
return obj;
}
void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = master->driver_priv;
drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
struct drm_gem_object *obj;
struct drm_radeon_gem_object *obj_priv;
/* update front_pitch_offset and back_pitch_offset */
obj = gem_object_get(dev, sarea_priv->front_handle);
if (obj) {
obj_priv = obj->driver_private;
dev_priv->front_offset = obj_priv->bo->offset;
dev_priv->front_pitch_offset = (((sarea_priv->front_pitch / 64) << 22) |
((obj_priv->bo->offset
+ dev_priv->fb_location) >> 10));
drm_gem_object_unreference(obj);
}
obj = gem_object_get(dev, sarea_priv->back_handle);
if (obj) {
obj_priv = obj->driver_private;
dev_priv->back_offset = obj_priv->bo->offset;
dev_priv->back_pitch_offset = (((sarea_priv->back_pitch / 64) << 22) |
((obj_priv->bo->offset
+ dev_priv->fb_location) >> 10));
drm_gem_object_unreference(obj);
}
dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
}

1
linux-core/radeon_i2c.c
View file

@ -154,7 +154,6 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
return NULL;
i2c->adapter.owner = THIS_MODULE;
i2c->adapter.id = I2C_HW_B_RADEON;
i2c->adapter.algo_data = &i2c->algo;
i2c->dev = dev;
i2c->algo.setsda = set_data;

151
shared-core/radeon_drm.h
View file

@ -453,18 +453,8 @@ typedef struct {
int pfCurrentPage; /* which buffer is being displayed? */
int crtc2_base; /* CRTC2 frame offset */
int tiling_enabled; /* set by drm, read by 2d + 3d clients */
unsigned int last_fence;
uint32_t front_handle;
uint32_t back_handle;
uint32_t depth_handle;
uint32_t front_pitch;
uint32_t back_pitch;
uint32_t depth_pitch;
} drm_radeon_sarea_t;
/* WARNING: If you change any of these defines, make sure to change the
* defines in the Xserver file (xf86drmRadeon.h)
*
@ -502,18 +492,16 @@ typedef struct {
#define DRM_RADEON_SETPARAM 0x19
#define DRM_RADEON_SURF_ALLOC 0x1a
#define DRM_RADEON_SURF_FREE 0x1b
#define DRM_RADEON_GEM_INFO 0x1c
#define DRM_RADEON_GEM_CREATE 0x1d
#define DRM_RADEON_GEM_MMAP 0x1e
#define DRM_RADEON_GEM_PIN 0x1f
#define DRM_RADEON_GEM_UNPIN 0x20
#define DRM_RADEON_GEM_PREAD 0x21
#define DRM_RADEON_GEM_PWRITE 0x22
#define DRM_RADEON_GEM_SET_DOMAIN 0x23
#define DRM_RADEON_GEM_WAIT_RENDERING 0x24
#define DRM_RADEON_CS 0x26
/* KMS ioctl */
#define DRM_RADEON_GEM_INFO 0x1c
#define DRM_RADEON_GEM_CREATE 0x1d
#define DRM_RADEON_GEM_MMAP 0x1e
#define DRM_RADEON_GEM_PREAD 0x21
#define DRM_RADEON_GEM_PWRITE 0x22
#define DRM_RADEON_GEM_SET_DOMAIN 0x23
#define DRM_RADEON_GEM_WAIT_IDLE 0x24
#define DRM_RADEON_CS 0x26
#define DRM_RADEON_INFO 0x27
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
@ -710,8 +698,7 @@ typedef struct drm_radeon_indirect {
#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
#define RADEON_PARAM_KERNEL_MM 16
#define RADEON_PARAM_DEVICE_ID 17
#define RADEON_PARAM_DEVICE_ID 16
typedef struct drm_radeon_getparam {
int param;
@ -763,11 +750,9 @@ typedef struct drm_radeon_setparam {
#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
#define RADEON_SETPARAM_MM_INIT 7 /* Initialise the mm */
/* 1.14: Clients can allocate/free a surface
*/
typedef struct drm_radeon_surface_alloc {
@ -783,61 +768,51 @@ typedef struct drm_radeon_surface_free {
#define DRM_RADEON_VBLANK_CRTC1 1
#define DRM_RADEON_VBLANK_CRTC2 2
#define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain
#define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed
#define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain
/*
* Kernel modesetting world below.
*/
#define RADEON_GEM_DOMAIN_CPU 0x1
#define RADEON_GEM_DOMAIN_GTT 0x2
#define RADEON_GEM_DOMAIN_VRAM 0x4
/* return to userspace start/size of gtt and vram apertures */
struct drm_radeon_gem_info {
uint64_t gart_start;
uint64_t gart_size;
uint64_t vram_start;
uint64_t vram_size;
uint64_t vram_visible;
uint64_t gart_size;
uint64_t vram_size;
uint64_t vram_visible;
};
#define RADEON_GEM_NO_BACKING_STORE 1
struct drm_radeon_gem_create {
uint64_t size;
uint64_t alignment;
uint32_t handle;
uint32_t initial_domain; // to allow VRAM to be created
uint32_t no_backing_store; // for VRAM objects - select whether they need backing store
// pretty much front/back/depth don't need it - other things do
uint64_t size;
uint64_t alignment;
uint32_t handle;
uint32_t initial_domain;
uint32_t flags;
};
struct drm_radeon_gem_mmap {
uint32_t handle;
uint32_t pad;
uint64_t offset;
uint64_t size;
uint64_t addr_ptr;
uint32_t handle;
uint32_t pad;
uint64_t offset;
uint64_t size;
uint64_t addr_ptr;
};
struct drm_radeon_gem_set_domain {
uint32_t handle;
uint32_t read_domains;
uint32_t write_domain;
uint32_t handle;
uint32_t read_domains;
uint32_t write_domain;
};
struct drm_radeon_gem_wait_rendering {
uint32_t handle;
};
struct drm_radeon_gem_pin {
uint32_t handle;
uint32_t pin_domain;
uint64_t alignment;
uint64_t offset;
};
struct drm_radeon_gem_unpin {
uint32_t handle;
uint32_t pad;
struct drm_radeon_gem_wait_idle {
uint32_t handle;
uint32_t pad;
};
struct drm_radeon_gem_busy {
uint32_t handle;
uint32_t busy;
uint32_t handle;
uint32_t busy;
};
struct drm_radeon_gem_pread {
@ -849,7 +824,8 @@ struct drm_radeon_gem_pread {
/** Length of data to read */
uint64_t size;
/** Pointer to write the data into. */
uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
/* void *, but pointers are not 32/64 compatible */
uint64_t data_ptr;
};
struct drm_radeon_gem_pwrite {
@ -861,28 +837,43 @@ struct drm_radeon_gem_pwrite {
/** Length of data to write */
uint64_t size;
/** Pointer to read the data from. */
uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
/* void *, but pointers are not 32/64 compatible */
uint64_t data_ptr;
};
/* New interface which obsolete all previous interface.
*/
#define RADEON_CHUNK_ID_RELOCS 0x01
#define RADEON_CHUNK_ID_IB 0x02
#define RADEON_CHUNK_ID_RELOCS 0x01
#define RADEON_CHUNK_ID_IB 0x02
struct drm_radeon_cs_chunk {
uint32_t chunk_id;
uint32_t length_dw;
uint64_t chunk_data;
uint32_t chunk_id;
uint32_t length_dw;
uint64_t chunk_data;
};
struct drm_radeon_cs_reloc {
uint32_t handle;
uint32_t read_domains;
uint32_t write_domain;
uint32_t flags;
};
struct drm_radeon_cs {
uint32_t num_chunks;
uint32_t cs_id;
uint64_t chunks; /* this points to uint64_t * which point to
cs chunks */
uint32_t num_chunks;
uint32_t cs_id;
/* this points to uint64_t * which point to cs chunks */
uint64_t chunks;
/* updates to the limits after this CS ioctl */
uint64_t gart_limit;
uint64_t vram_limit;
};
#define RADEON_INFO_DEVICE_ID 0x00
#define RADEON_INFO_NUM_GB_PIPES 0x01
struct drm_radeon_info {
uint32_t request;
uint32_t pad;
uint64_t value;
};
#endif

13
shared-core/radeon_drv.h
View file

@ -1662,18 +1662,11 @@ extern uint64_t radeon_evict_flags(struct drm_buffer_object *bo);
static inline int radeon_update_breadcrumb(struct drm_device *dev)
{
struct drm_radeon_private *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv;
++dev_priv->counter;
if (dev_priv->counter > BREADCRUMB_MASK)
dev_priv->counter = 1;
if (dev->primary->master) {
master_priv = dev->primary->master->driver_priv;
if (master_priv->sarea_priv)
master_priv->sarea_priv->last_fence = dev_priv->counter;
}
return dev_priv->counter;
}
@ -1713,16 +1706,12 @@ extern void radeon_gem_free_object(struct drm_gem_object *obj);
extern int radeon_gem_init_object(struct drm_gem_object *obj);
extern int radeon_gem_mm_init(struct drm_device *dev);
extern void radeon_gem_mm_fini(struct drm_device *dev);
extern int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int radeon_gem_object_pin(struct drm_gem_object *obj,
uint32_t alignment, uint32_t pin_domain);
int radeon_gem_object_unpin(struct drm_gem_object *obj);
int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int radeon_gem_wait_rendering(struct drm_device *dev, void *data,
int radeon_gem_wait_idle(struct drm_device *dev, void *data,
struct drm_file *file_priv);
struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
int initial_domain, bool discardable);

14
shared-core/radeon_state.c
View file

@ -2224,9 +2224,6 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
if (dev_priv->mm.vram_offset)
radeon_gem_update_offsets(dev, file_priv->master);
radeon_cp_dispatch_swap(dev, file_priv->master);
sarea_priv->ctx_owner = 0;
@ -3121,9 +3118,6 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
case RADEON_PARAM_NUM_GB_PIPES:
value = dev_priv->num_gb_pipes;
break;
case RADEON_PARAM_KERNEL_MM:
value = dev_priv->mm_enabled;
break;
default:
DRM_DEBUG( "Invalid parameter %d\n", param->param );
return -EINVAL;
@ -3185,10 +3179,6 @@ static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_fil
case RADEON_SETPARAM_VBLANK_CRTC:
return radeon_vblank_crtc_set(dev, sp->value);
break;
case RADEON_SETPARAM_MM_INIT:
dev_priv->user_mm_enable = true;
dev_priv->new_memmap = true;
return radeon_gem_mm_init(dev);
default:
DRM_DEBUG("Invalid parameter %d\n", sp->param);
return -EINVAL;
@ -3284,12 +3274,10 @@ struct drm_ioctl_desc radeon_ioctls[] = {
DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_GEM_PIN, radeon_gem_pin_ioctl, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_GEM_UNPIN, radeon_gem_unpin_ioctl, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_RENDERING, radeon_gem_wait_rendering, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
};