Commit graph

1214 commits

Author SHA1 Message Date
Ben Skeggs
e26ec51146 nouveau: small RAMFC cleanups 2007-06-29 14:20:50 +10:00
Ben Skeggs
1c32fecd6d nouveau: Hack around possible Xv blit adaptor breakage 2007-06-28 21:01:17 +10:00
Ben Skeggs
2dd85772aa nouveau/nv10: Fix earlier NV1x chips
Can't use nv04 code for them, since an extra field was inserted into
RAMFC after DMA_PUT/GET.
2007-06-28 04:23:17 +10:00
Ben Skeggs
68ecf61647 nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit 2007-06-28 03:26:44 +10:00
Ben Skeggs
18a6d1c9c3 nouveau: simplify PRAMIN access 2007-06-28 03:26:44 +10:00
Ben Skeggs
38617b6a26 nouveau: name some regs 2007-06-28 03:26:44 +10:00
Ben Skeggs
ce0d528d3c nouveau/nv50: skeletal backend 2007-06-28 03:26:43 +10:00
Ben Skeggs
695599f18d nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)
For various reasons, this ioctl was a bad idea.

At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.

However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers).  Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28 03:26:43 +10:00
Ben Skeggs
4f2dd78ff3 nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks 2007-06-28 03:04:48 +10:00
Thomas Hellstrom
9b9a127ed0 More 64-bit padding. 2007-06-26 23:25:40 +02:00
Ian Romanick
5c27f8a70e Add support SiS based XGI chips to SiS DRM. 2007-06-26 09:51:55 -07:00
Ben Skeggs
9f617522d9 nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303 2007-06-25 01:57:57 +10:00
Ben Skeggs
3dfc13e2da nouveau: kill some dead code 2007-06-24 19:00:44 +10:00
Ben Skeggs
5f05cd7086 nouveau: NV04/NV10/NV20 PGRAPH engtab functions
NV04/NV10 load_context()/save_context() are stubs.  I don't know enough about
how they work to implement them sanely.  The "old" context_switch() code
remains hooked up, so it shouldn't break anything.

NV20 will probably break if load_context() works.  No inital context values
are filled in, so when the first channel is created PGRAPH will probably end
up having its state zeroed.  Some setup from nv20_graph_init() will probably
need to be moved to the per-channel context setup.
2007-06-24 19:00:26 +10:00
Ben Skeggs
5d55b0655c nouveau: NV3X PGRAPH engtab functions 2007-06-24 18:58:38 +10:00
Ben Skeggs
341bc78207 nouveau: NV1X/2X/3X PFIFO engtab functions
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size.
2007-06-24 18:58:14 +10:00
Ben Skeggs
05d86d950a nouveau: NV04 PFIFO engtab functions 2007-06-24 18:57:09 +10:00
Ben Skeggs
acb710d1a5 nouveau: NV4X PGRAPH engtab functions 2007-06-24 18:56:40 +10:00
Ben Skeggs
f2e64d5276 nouveau: NV4X PFIFO engtab functions 2007-06-24 18:56:01 +10:00
Ben Skeggs
0afb3b518e nouveau: split PFIFO/PGRAPH context creation 2007-06-24 18:55:23 +10:00
Ben Skeggs
9dbf322d26 nouveau: (mostly) hook up put_base again 2007-06-24 18:55:06 +10:00
Ben Skeggs
24b71c318a nouveau: prototype PFIFO/PGRAPH engtab API 2007-06-24 18:54:51 +10:00
Ben Skeggs
5c7c07fd49 nouveau: rename engtab functions 2007-06-24 18:54:36 +10:00
Jesse Barnes
7f2a1cf275 Merge branch 'vblank-rework' into vblank 2007-06-22 11:12:02 -07:00
Jesse Barnes
97dcd7fd25 more vblank rework
- use a timer for disabling vblank events to avoid enable/disable calls too
    often
  - make i915 work with pre-965 chips again (would like to structure this
    better, but this hack works on my test system)
2007-06-22 11:06:51 -07:00
Michel Dänzer
068ffc1e1b radeon: Acknowledge all interrupts we're interested in.
Failure to do so was probably the root cause of fd.o bug 11287.
2007-06-22 11:55:26 +02:00
Michel Dänzer
6e2cd7c163 drm_modeset_ctl_t fixes.
s/u64/drm_u64_t/ to allow userspace code using drm.h to compile.

Move 64 bit arg member to the beginning to avoid alignment issues with 32
bit userspace on 64 bit kernels.
2007-06-22 11:44:19 +02:00
Michel Dänzer
b8dd314875 Remove mask parameter from radeon_acknowledge_irqs().
Simply always acknowledge all interrupts we're interested in, to avoid hard
hangs when an unexpected interrupt is flagged.
2007-06-22 11:42:54 +02:00
Jesse Barnes
24c09faec1 Merge branch 'vblank-rework' into vblank 2007-06-21 15:26:34 -07:00
Jesse Barnes
afe842297f RADEON: fix race in vblank interrupt handling
It's possible that we disable vblank interrupts and clear the
corresponding flag in irq_enable_reg, but receive an interrupt at just
the wrong time, causing us to not ack it properly, nor report to the
core kernel that it was handled.  Fix that case by always handling
vblank interrupts, even if the irq_enable_reg field is clear.
2007-06-21 15:23:20 -07:00
Oliver McFadden
40f6a696cb r300: Synchronized the register defines file; documentation changes. 2007-06-21 14:35:11 +00:00
Oliver McFadden
213732af43 r300: Allow writes to R300_VAP_PVS_WAITIDLE. 2007-06-21 14:32:58 +00:00
Jesse Barnes
2d24455ed8 Remove broken CRTC enable checks and incorrect user irq enable in set_pipe
routine.
2007-06-18 17:43:58 -07:00
Michel Dänzer
d8ed021d29 radeon: VBlank rework fixups.
Fix range of frame counter registers.

Use DRM_ERR() instead of Linux specific error codes in shared code.

Remove duplicate register definitions and superfluous local variables.
2007-06-18 13:10:37 +02:00
Oliver McFadden
215787e429 r300: Registers 0x2220-0x2230 are known as R300_VAP_CLIP_X_0-R300_VAP_CLIP_Y_1. 2007-06-18 08:42:46 +00:00
Oliver McFadden
8038e7b60f r300: Synchronized the register defines file again. 2007-06-18 08:36:50 +00:00
Jesse Barnes
741d1c8031 Remove broken crtc enable checks, radeon does it slightly differently
(this makes get_vblank_counter return an actual value).
2007-06-15 17:06:46 -07:00
Jesse Barnes
b6610363e3 First cut at radeon support for the vblank rework. 2007-06-15 11:21:57 -07:00
Michel Dänzer
3d5d41fa98 i915: Fix handling of breadcrumb counter wraparounds. 2007-06-15 17:13:11 +02:00
Michel Dänzer
82e2c3304d Wake up vblank waitqueue in drm_handle_vblank(). 2007-06-15 10:25:50 +02:00
Michel Dänzer
914a810a82 i915: Fix tests for vblank interrupts being enabled on CRTC by X server. 2007-06-15 10:21:44 +02:00
Michel Dänzer
1000d88ddf Fix memory leaks in vblank error paths.
Also use drm_calloc instead of drm_alloc and memset, and use the size of the
struct instead of the size of the pointer for allocation...
2007-06-15 10:10:33 +02:00
Jesse Barnes
b06268294a Comment new vblank routines and fixup several issues:
- use correct refcount variable in get/put routines
  - extract counter update from drm_vblank_get
  - make signal handling callback per-crtc
  - update interrupt handling logic, drivers should use drm_handle_vblank
  - move wakeup and counter update logic to new drm_handle_vblank routine
  - fixup usage of get/put in light of counter update extraction
  - fix longstanding bug in signal code, update pending counter only
    *after* we're sure we'll setup signal handling
2007-06-14 11:32:31 -07:00
Jesse Barnes
1a4b9294a2 Remove unnecessary (and uncommented!) read barrier from the interrupt
path.  It doesn't appear to serve any useful purpose.
2007-06-12 16:29:09 -07:00
Jesse Barnes
ca47fa90b7 Update vblank code:
- move pre/post modeset ioctl to core
  - fixup i915 buffer swap
  - fix outstanding signal count code
  - create new core vblank init routine
  - test (works with glxgears)
  - simplify i915 interrupt handler
2007-06-12 13:35:41 -07:00
Jesse Barnes
db689c7b95 Initial checkin of vblank rework. Code attempts to reduce the number
of vblank interrupt in order to save power.
2007-06-12 10:44:21 -07:00
Thomas Hellstrom
f984b1b8d1 Fix some obvious bugs. 2007-06-12 12:30:33 +02:00
Thomas Hellstrom
b6b5df24b9 Try to make buffer object / fence object ioctl args 64-bit safe.
Introduce tile members for future tiled buffer support.
Allow user-space to explicitly define a fence-class.
Remove the implicit fence-class mechanism.
64-bit wide buffer object flag member.
2007-06-12 12:21:38 +02:00
Oliver McFadden
3181573073 r300: Added the CP maximum fetch size and ring rptr update variables. 2007-06-08 19:40:57 +00:00
Oliver McFadden
39625f9621 r300: Small correction to the previous commit. 2007-06-05 19:19:42 +00:00