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amdgpu: Add queue priority and secure flags support for user queues
This patch extends the user queue creation API to support: 1. Queue priority levels (normal low, low, normal high, high) - High priority is restricted to admin-only 2. Secure queue flag for protected content access The changes include: - Adding a `flags` parameter to `amdgpu_create_userqueue()` - Defining priority and security flags in `amdgpu_drm.h` - Updating the `drm_amdgpu_userq_in` struct to replace padding with flags - Documenting the new flags field Related driver patches provided by Alex: https://lists.freedesktop.org/archives/amd-gfx/2025-April/122782.html https://lists.freedesktop.org/archives/amd-gfx/2025-April/122780.html https://lists.freedesktop.org/archives/amd-gfx/2025-April/122786.html Cc: Koenig, Christian <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse.Zhang <Jesse.zhang@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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3 changed files with 18 additions and 1 deletions
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@ -2026,6 +2026,7 @@ int amdgpu_create_userqueue(amdgpu_device_handle dev,
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uint64_t wptr_va,
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uint64_t rptr_va,
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void *mqd_in,
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uint32_t flags,
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uint32_t *queue_id);
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/**
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@ -37,6 +37,7 @@ amdgpu_create_userqueue(amdgpu_device_handle dev,
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uint64_t wptr_va,
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uint64_t rptr_va,
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void *mqd_in,
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uint32_t flags,
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uint32_t *queue_id)
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{
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int ret;
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@ -75,6 +76,7 @@ amdgpu_create_userqueue(amdgpu_device_handle dev,
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userq.in.mqd = (uint64_t)mqd_in;
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userq.in.mqd_size = mqd_size;
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userq.in.flags = flags;
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ret = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ,
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&userq, sizeof(userq));
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@ -327,6 +327,16 @@ union drm_amdgpu_ctx {
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#define AMDGPU_USERQ_OP_CREATE 1
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#define AMDGPU_USERQ_OP_FREE 2
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/* queue priority levels */
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */
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/* for queues that need access to protected content */
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2)
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/*
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* This structure is a container to pass input configuration
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* info for all supported userqueue related operations.
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@ -353,7 +363,11 @@ struct drm_amdgpu_userq_in {
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* and doorbell_offset in the doorbell bo.
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*/
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__u32 doorbell_offset;
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__u32 _pad;
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/**
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* @flags: flags used for queue parameters
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*/
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__u32 flags;
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/**
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* @queue_va: Virtual address of the GPU memory which holds the queue
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* object. The queue holds the workload packets.
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