mirror of
https://gitlab.freedesktop.org/mesa/drm.git
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fdf384d4b5
This patch extends the user queue creation API to support: 1. Queue priority levels (normal low, low, normal high, high) - High priority is restricted to admin-only 2. Secure queue flag for protected content access The changes include: - Adding a `flags` parameter to `amdgpu_create_userqueue()` - Defining priority and security flags in `amdgpu_drm.h` - Updating the `drm_amdgpu_userq_in` struct to replace padding with flags - Documenting the new flags field Related driver patches provided by Alex: https://lists.freedesktop.org/archives/amd-gfx/2025-April/122782.html https://lists.freedesktop.org/archives/amd-gfx/2025-April/122780.html https://lists.freedesktop.org/archives/amd-gfx/2025-April/122786.html Cc: Koenig, Christian <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse.Zhang <Jesse.zhang@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
123 lines
3.2 KiB
C
123 lines
3.2 KiB
C
/*
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* Copyright 2024 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <string.h>
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#include <errno.h>
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#include "xf86drm.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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drm_public int
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amdgpu_create_userqueue(amdgpu_device_handle dev,
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uint32_t ip_type,
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uint32_t doorbell_handle,
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uint32_t doorbell_offset,
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uint64_t queue_va,
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uint64_t queue_size,
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uint64_t wptr_va,
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uint64_t rptr_va,
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void *mqd_in,
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uint32_t flags,
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uint32_t *queue_id)
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{
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int ret;
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union drm_amdgpu_userq userq;
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uint64_t mqd_size;
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if (!dev)
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return -EINVAL;
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switch (ip_type) {
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case AMDGPU_HW_IP_GFX:
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mqd_size = sizeof(struct drm_amdgpu_userq_mqd_gfx11);
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break;
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case AMDGPU_HW_IP_DMA:
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mqd_size = sizeof(struct drm_amdgpu_userq_mqd_sdma_gfx11);
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break;
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case AMDGPU_HW_IP_COMPUTE:
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mqd_size = sizeof(struct drm_amdgpu_userq_mqd_compute_gfx11);
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break;
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default:
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return -EINVAL;
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}
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memset(&userq, 0, sizeof(userq));
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userq.in.op = AMDGPU_USERQ_OP_CREATE;
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userq.in.ip_type = ip_type;
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userq.in.doorbell_handle = doorbell_handle;
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userq.in.doorbell_offset = doorbell_offset;
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userq.in.queue_va = queue_va;
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userq.in.queue_size = queue_size;
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userq.in.wptr_va = wptr_va;
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userq.in.rptr_va = rptr_va;
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userq.in.mqd = (uint64_t)mqd_in;
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userq.in.mqd_size = mqd_size;
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userq.in.flags = flags;
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ret = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ,
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&userq, sizeof(userq));
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*queue_id = userq.out.queue_id;
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return ret;
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}
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drm_public int
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amdgpu_free_userqueue(amdgpu_device_handle dev, uint32_t queue_id)
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{
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union drm_amdgpu_userq userq;
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memset(&userq, 0, sizeof(userq));
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userq.in.op = AMDGPU_USERQ_OP_FREE;
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userq.in.queue_id = queue_id;
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return drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ,
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&userq, sizeof(userq));
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}
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drm_public int
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amdgpu_userq_signal(amdgpu_device_handle dev,
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struct drm_amdgpu_userq_signal *signal_data)
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{
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int r;
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ_SIGNAL,
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signal_data, sizeof(struct drm_amdgpu_userq_signal));
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return r;
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}
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drm_public int
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amdgpu_userq_wait(amdgpu_device_handle dev,
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struct drm_amdgpu_userq_wait *wait_data)
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{
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int r;
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ_WAIT,
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wait_data, sizeof(struct drm_amdgpu_userq_wait));
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return r;
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}
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