mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-16 10:58:09 +02:00
Checkpoint commit, I'm about to throw all this code away...
This commit is contained in:
Gareth Hughes
parent
b6f4c2f7bf
commit
b5366b9789
3 changed files with 166 additions and 128 deletions
218
linux/mga_dma.c
218
linux/mga_dma.c
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@ -1017,7 +1017,6 @@ int mga_flush_ioctl(struct inode *inode, struct file *filp,
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* ****************************************************************
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*/
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static unsigned long mga_alloc_page( void )
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{
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unsigned long address;
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@ -1083,26 +1082,33 @@ int mga_do_dma_idle( drm_mga_private_t *dev_priv )
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int mga_do_dma_reset( drm_mga_private_t *dev_priv )
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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unsigned long flags;
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DRM_DEBUG( "%s\n", __FUNCTION__ );
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spin_lock_irqsave( &primary->lock, flags );
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/* The primary DMA stream should look like new right about now.
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*/
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dev_priv->prim.head = 0;
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dev_priv->prim.tail = 0;
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dev_priv->prim.wrap = 0;
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dev_priv->prim.space = dev_priv->prim.size - MGA_DMA_SOFTRAP_SIZE;
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dev_priv->prim.last_flush = 0;
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primary->head = 0;
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primary->tail = 0;
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primary->wrap = 0;
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primary->space = primary->size - MGA_DMA_SOFTRAP_SIZE;
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primary->last_flush = 0;
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/* FIXME: Reset counters, buffer ages etc...
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*/
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clear_bit( MGA_DMA_FLUSH, &dev_priv->prim.state );
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clear_bit( MGA_DMA_WRAP, &dev_priv->prim.state );
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clear_bit( MGA_DMA_FLUSH, &primary->state );
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clear_bit( MGA_DMA_WRAP, &primary->state );
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set_bit( MGA_DMA_IDLE, &dev_priv->prim.state );
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set_bit( MGA_DMA_IDLE, &primary->state );
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/* FIXME: What else do we need to reinitialize? WARP stuff?
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*/
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spin_unlock_irqrestore( &dev_priv->prim.lock, flags );
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return 0;
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}
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@ -1150,32 +1156,37 @@ int mga_do_engine_reset( drm_mga_private_t *dev_priv )
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/* The primary DMA stream *MUST* be idle before this is called. Use
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* mga_do_dma_idle() above if required.
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*
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* The mga_dma_lock IRQ-safe spinlock *MUST* be held before this is
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* called. You have been warned...
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*/
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static inline void mga_do_dma( drm_mga_private_t *dev_priv,
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u32 head, u32 tail )
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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DRM_DEBUG( "%s:\n", __FUNCTION__ );
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DRM_INFO( "%s:\n", __FUNCTION__ );
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/* Only flush the primary DMA stream if there are new commands.
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*/
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if ( head == tail ) {
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DRM_DEBUG( " bailing out...\n" );
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clear_bit( 0, &dev_priv->dma_flag );
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DRM_INFO( " bailing out...\n" );
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return;
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}
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DRM_DEBUG( " head = 0x%08x 0x%04x\n",
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head, head - dev_priv->primary->offset );
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DRM_DEBUG( " tail = 0x%08x 0x%04x\n",
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tail, tail - dev_priv->primary->offset );
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if ( tail <= head ) {
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u32 tmp, *fuck = 0x12345678;
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DRM_ERROR( "FUCK ME DEAD\n" );
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tmp = *fuck;
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if ( tail < head ) {
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DRM_ERROR( " head = 0x%08x 0x%04x\n",
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head, head - dev_priv->primary->offset );
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DRM_ERROR( " tail = 0x%08x 0x%04x\n",
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tail, tail - dev_priv->primary->offset );
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DRM_ERROR( "*** oops, we messed up ***\n" );
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}
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DRM_INFO( " status = 0x%08x\n", MGA_READ( MGA_STATUS ) );
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DRM_INFO( " head = 0x%08x 0x%04x\n",
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head, head - dev_priv->primary->offset );
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DRM_INFO( " tail = 0x%08x 0x%04x\n",
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tail, tail - dev_priv->primary->offset );
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clear_bit( MGA_DMA_IDLE, &primary->state );
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mga_flush_write_combine();
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@ -1183,9 +1194,7 @@ static inline void mga_do_dma( drm_mga_private_t *dev_priv,
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MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
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MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
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clear_bit( 0, &dev_priv->dma_flag );
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DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
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DRM_INFO( "%s: done.\n", __FUNCTION__ );
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}
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void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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@ -1193,12 +1202,7 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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u32 head, tail;
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DMA_LOCALS;
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DRM_DEBUG( "%s:\n", __FUNCTION__ );
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if ( test_and_set_bit( 0, &dev_priv->dma_flag ) ) {
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DRM_ERROR( "wtf???\n" );
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return;
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}
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DRM_INFO( "%s:\n", __FUNCTION__ );
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/* Flushing the primary DMA stream will always result in this
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* function being called, even if there are no new commands.
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@ -1210,8 +1214,7 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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/* Only flush the primary DMA stream if there are new commands.
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*/
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if ( primary->tail == primary->last_flush ) {
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DRM_DEBUG( " bailing out...\n" );
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clear_bit( 0, &dev_priv->dma_flag );
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DRM_INFO( " bailing out...\n" );
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return;
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}
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@ -1236,24 +1239,19 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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/* Kick off the DMA transfer.
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*/
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mga_do_dma( dev_priv, head, tail );
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DRM_INFO( "%s: done.\n", __FUNCTION__ );
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}
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void mga_do_dma_wrap( drm_mga_private_t *dev_priv )
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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u32 head, tail;
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DRM_DEBUG( "%s:\n", __FUNCTION__ );
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if ( test_and_set_bit( 0, &dev_priv->dma_flag ) ) {
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DRM_ERROR( "wtf???\n" );
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return;
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}
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DRM_INFO( "%s:\n", __FUNCTION__ );
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/* Only wrap the primary DMA stream if we have to.
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*/
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if ( !primary->wrap ) {
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DRM_DEBUG( " bailing out...\n" );
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clear_bit( 0, &dev_priv->dma_flag );
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DRM_INFO( " bailing out...\n" );
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return;
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}
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@ -1271,6 +1269,7 @@ void mga_do_dma_wrap( drm_mga_private_t *dev_priv )
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/* Kick off the DMA transfer.
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*/
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mga_do_dma( dev_priv, head, tail );
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DRM_INFO( "%s: done.\n", __FUNCTION__ );
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}
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void mga_dma_wrap_or_wait( drm_mga_private_t *dev_priv, int n )
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@ -1317,28 +1316,9 @@ void mga_dma_wrap_or_wait( drm_mga_private_t *dev_priv, int n )
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;
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mga_do_dma_flush( dev_priv );
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primary->space = (primary->head - primary->tail);
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}
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}
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void mga_update_primary_snapshot( drm_mga_private_t *dev_priv )
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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if ( !primary->wrap ) {
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primary->space = primary->size - primary->tail;
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} else {
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primary->space = (primary->head - primary->tail -
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dev_priv->primary->offset);
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}
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/* Reserve space for SOFTRAP interrupt generator at the end of
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* the current chunk of our primary DMA buffer.
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*/
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primary->space -= MGA_DMA_SOFTRAP_SIZE;
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}
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/* ================================================================
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* DMA interrupt handling
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@ -1349,6 +1329,7 @@ static void mga_dma_service( int irq, void *device, struct pt_regs *regs )
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drm_device_t *dev = (drm_device_t *)device;
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drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
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DRM_INFO( " *** took interrupt\n" );
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atomic_inc( &dev->total_irq );
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/* Verify the interrupt we're servicing is actually the one we
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@ -1365,43 +1346,47 @@ static void mga_dma_service( int irq, void *device, struct pt_regs *regs )
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static void mga_dma_task_queue( void *dev )
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{
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mga_dma_schedule( dev, 0 );
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mga_dma_schedule( dev );
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}
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int mga_dma_schedule( drm_device_t *dev, int locked )
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int mga_dma_schedule( drm_device_t *dev )
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{
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drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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DRM_DEBUG( "%s: prim=0x%x low=0x%x\n",
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__FUNCTION__,
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dev_priv->prim.tail - dev_priv->prim.last_flush,
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dev_priv->prim.low_mark);
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unsigned long flags;
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if ( test_and_set_bit( 0, &dev_priv->interrupt_flag ) ) {
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DRM_ERROR( "wtf???\n" );
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return -EBUSY;
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}
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spin_lock_irqsave( &primary->lock, flags );
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DRM_INFO( "spin_lock() in %s\n", __FUNCTION__ );
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DRM_INFO( "%s: prim=0x%x low=0x%x\n",
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__FUNCTION__,
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primary->tail - primary->last_flush,
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primary->low_mark );
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set_bit( MGA_DMA_IDLE, &primary->state );
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primary->head = primary->last_flush;
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if ( dev_priv->prim.wrap ) {
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DRM_DEBUG( " wrapping primary DMA...\n" );
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if ( primary->wrap ) {
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DRM_INFO( " wrapping primary DMA...\n" );
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mga_do_dma_wrap( dev_priv );
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} else if ( test_bit( MGA_DMA_FLUSH, &dev_priv->prim.state ) ) {
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DRM_DEBUG( " forcing primary DMA...\n" );
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} else if ( test_bit( MGA_DMA_FLUSH, &primary->state ) ) {
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DRM_INFO( " forcing primary DMA...\n" );
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mga_do_dma_flush( dev_priv );
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} else if ( dev_priv->prim.tail - dev_priv->prim.last_flush >=
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dev_priv->prim.low_mark ) {
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DRM_DEBUG( " flushing primary DMA...\n" );
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#if 0
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} else if ( primary->tail - primary->last_flush >=
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primary->low_mark ) {
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DRM_INFO( " flushing primary DMA...\n" );
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mga_do_dma_flush( dev_priv );
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#endif
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} else {
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DRM_DEBUG( " going idle...\n" );
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DRM_INFO( " going idle...\n" );
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}
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DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
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clear_bit( 0, &dev_priv->interrupt_flag );
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DRM_INFO( "%s: done.\n", __FUNCTION__ );
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DRM_INFO( "spin_unlock() in %s\n", __FUNCTION__ );
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spin_unlock_irqrestore( &primary->lock, flags );
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return 0;
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}
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@ -1519,10 +1504,13 @@ static drm_buf_t *mga_freelist_get( drm_device_t *dev )
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drm_mga_private_t *dev_priv = dev->dev_private;
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drm_mga_freelist_t *next;
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drm_mga_freelist_t *prev;
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spin_lock_bh( &dev_priv->prim.lock );
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DRM_DEBUG( "spin_lock_bh() in %s\n", __FUNCTION__ );
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DRM_DEBUG( "%s: tail=0x%x status=0x%x\n",
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__FUNCTION__, dev_priv->tail->age,
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dev_priv->prim.status[1] );
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#if 0
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mga_freelist_print( dev );
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#endif
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@ -1533,9 +1521,15 @@ static drm_buf_t *mga_freelist_get( drm_device_t *dev )
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next->prev = next->next = NULL;
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dev_priv->tail = prev;
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next->age = MGA_BUFFER_USED;
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DRM_DEBUG( "spin_unlock_bh() in %s\n", __FUNCTION__ );
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spin_unlock_bh( &dev_priv->prim.lock );
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return next->buf;
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}
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DRM_DEBUG( "spin_unlock_bh() in %s\n", __FUNCTION__ );
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spin_unlock_bh( &dev_priv->prim.lock );
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DRM_ERROR( "returning NULL!\n" );
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return NULL;
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}
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@ -1676,7 +1670,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
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MGA_WRITE( MGA_PRIMPTR,
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virt_to_bus((void *)dev_priv->prim.status_page) |
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MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
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0 /*MGA_PRIMPTREN1*/ ); /* DWGSYNC */
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MGA_PRIMPTREN1 ); /* DWGSYNC */
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#endif
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dev_priv->prim.start = (u8 *)dev_priv->primary->handle;
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@ -1696,6 +1690,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
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set_bit( MGA_DMA_IDLE, &dev_priv->prim.state );
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spin_lock_init( &dev_priv->prim.lock );
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dev_priv->sarea_priv->last_dispatch = 0;
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dev_priv->prim.status[1] = 0;
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@ -1781,13 +1777,17 @@ int mga_dma_flush( struct inode *inode, struct file *filp,
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if ( copy_from_user( &lock, (drm_lock_t *)arg, sizeof(lock) ) )
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return -EFAULT;
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DRM_DEBUG( "%s: %s%s%s\n",
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DRM_INFO( "%s: %s%s%s\n",
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__FUNCTION__,
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(lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
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(lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
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(lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" );
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if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) {
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spin_lock_bh( &dev_priv->prim.lock );
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DRM_INFO( "spin_lock_bh() in %s\n", __FUNCTION__ );
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/* Force the flushing of any outstanding primary DMA
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* commands. We must flag this so the interrupt
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* handler can take appropriate action if the primary
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@ -1798,14 +1798,10 @@ int mga_dma_flush( struct inode *inode, struct file *filp,
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/* If the primary DMA stream is currently idle, do the
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* flush immediately.
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*/
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if ( MGA_DMA_IS_IDLE( dev_priv ) ) {
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if ( dev_priv->prim.wrap ) {
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mga_do_dma_wrap( dev_priv );
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} else {
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mga_do_dma_flush( dev_priv );
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}
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mga_update_primary_snapshot( dev_priv );
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}
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FLUSH_DMA();
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DRM_INFO( "spin_unlock_bh() in %s\n", __FUNCTION__ );
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spin_unlock_bh( &dev_priv->prim.lock );
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}
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if ( lock.flags & _DRM_LOCK_QUIESCENT ) {
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@ -1889,11 +1885,6 @@ int mga_irq_install( drm_device_t *dev, int irq )
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if ( 0 ) {
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int i;
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int ret;
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@ -1921,9 +1912,12 @@ if ( 0 ) {
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*/
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mga_do_wait_for_idle( dev_priv );
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for ( i = 0 ; i < 256 * 1024 ; i++ ) {
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for ( i = 0 ; i < 1 * 1024 ; i++ ) {
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DMA_LOCALS;
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spin_lock_bh( &dev_priv->prim.lock );
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DRM_DEBUG( "spin_lock_bh() in %s\n", __FUNCTION__ );
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BEGIN_DMA( 8 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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@ -1966,32 +1960,47 @@ if ( 0 ) {
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000 );
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udelay( 5 );
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ADVANCE_DMA();
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udelay( 5 );
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DRM_DEBUG( "spin_unlock_bh() in %s\n", __FUNCTION__ );
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spin_unlock_bh( &dev_priv->prim.lock );
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if ( (i & 0x7f) == 0x7f ) {
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DRM_INFO( "*** forcing flush now ***\n" );
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DRM_DEBUG( "*** forcing flush now ***\n" );
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if ( mga_do_wait_for_idle( dev_priv ) < 0 )
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return -EINVAL;
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spin_lock_bh( &dev_priv->prim.lock );
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DRM_DEBUG( "spin_lock_bh() in %s\n", __FUNCTION__ );
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mga_do_dma_flush( dev_priv );
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#if 0
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if ( mga_do_wait_for_idle( dev_priv ) < 0 )
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return -EINVAL;
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#endif
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DRM_DEBUG( "spin_unlock_bh() in %s\n", __FUNCTION__ );
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spin_unlock_bh( &dev_priv->prim.lock );
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}
|
||||
|
||||
udelay( 5 );
|
||||
}
|
||||
|
||||
/* Flush the primary DMA stream.
|
||||
*/
|
||||
mga_do_wait_for_idle( dev_priv );
|
||||
DRM_INFO( "*** forcing final flush now ***\n" );
|
||||
|
||||
DRM_DEBUG( "*** forcing final flush now ***\n" );
|
||||
|
||||
spin_lock_bh( &dev_priv->prim.lock );
|
||||
DRM_DEBUG( "spin_lock_bh() in %s\n", __FUNCTION__ );
|
||||
|
||||
mga_do_dma_flush( dev_priv );
|
||||
|
||||
DRM_DEBUG( "spin_unlock_bh() in %s\n", __FUNCTION__ );
|
||||
spin_unlock_bh( &dev_priv->prim.lock );
|
||||
|
||||
mga_do_wait_for_idle( dev_priv );
|
||||
|
||||
spin_lock_bh( &dev_priv->prim.lock );
|
||||
|
||||
DRM_DEBUG( "head = 0x%08x\n", dev_priv->prim.status[0] );
|
||||
DRM_DEBUG( "sync = 0x%08x\n", dev_priv->prim.status[1] );
|
||||
DRM_INFO( "\n" );
|
||||
|
|
@ -2001,6 +2010,7 @@ if ( 0 ) {
|
|||
DRM_INFO( "\n" );
|
||||
DRM_INFO( " irqs = %d\n", atomic_read( &dev->total_irq ) );
|
||||
|
||||
spin_unlock_bh( &dev_priv->prim.lock );
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ typedef struct drm_mga_primary_buffer {
|
|||
u32 high_mark;
|
||||
|
||||
unsigned long state;
|
||||
spinlock_t lock;
|
||||
} drm_mga_primary_buffer_t;
|
||||
|
||||
|
||||
|
|
@ -136,9 +137,6 @@ typedef struct drm_mga_private {
|
|||
|
||||
drm_mga_primary_buffer_t prim;
|
||||
|
||||
volatile long interrupt_flag; /* Interruption handler flag */
|
||||
volatile long dma_flag; /* DMA dispatch flag */
|
||||
|
||||
unsigned int warp_pipe;
|
||||
unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
|
||||
|
||||
|
|
@ -202,7 +200,7 @@ extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
|
|||
extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
|
||||
extern int mga_do_cleanup_dma( drm_device_t *dev );
|
||||
|
||||
extern int mga_dma_schedule( drm_device_t *dev, int locked );
|
||||
extern int mga_dma_schedule( drm_device_t *dev );
|
||||
extern void mga_dma_wrap_or_wait( drm_mga_private_t *dev_priv, int n );
|
||||
extern int mga_irq_uninstall( drm_device_t *dev );
|
||||
|
||||
|
|
@ -408,7 +406,7 @@ do { \
|
|||
if ( MGA_VERBOSE ) { \
|
||||
DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
|
||||
(n), __FUNCTION__ ); \
|
||||
DRM_INFO( " space=0x%x req=0x%x\n", \
|
||||
DRM_DEBUG( " space=0x%x req=0x%x\n", \
|
||||
dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
|
||||
} \
|
||||
if ( dev_priv->prim.space < (int)((n) * DMA_BLOCK_SIZE) ) { \
|
||||
|
|
@ -436,7 +434,6 @@ do { \
|
|||
DRM_INFO( "MAYBE_FLUSH_DMA() wrap at 0x%x\n", \
|
||||
dev_priv->prim.wrap ); \
|
||||
mga_do_dma_wrap( dev_priv ); \
|
||||
mga_update_primary_snapshot( dev_priv ); \
|
||||
} else if ( dev_priv->prim.tail - dev_priv->prim.last_flush >= \
|
||||
dev_priv->prim.mid_mark && \
|
||||
MGA_DMA_IS_IDLE( dev_priv ) ) { \
|
||||
|
|
@ -445,7 +442,17 @@ do { \
|
|||
dev_priv->prim.last_flush, \
|
||||
dev_priv->prim.mid_mark ); \
|
||||
mga_do_dma_flush( dev_priv ); \
|
||||
mga_update_primary_snapshot( dev_priv ); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define FLUSH_DMA() \
|
||||
do { \
|
||||
if ( MGA_DMA_IS_IDLE( dev_priv ) ) { \
|
||||
if ( dev_priv->prim.wrap ) { \
|
||||
mga_do_dma_wrap( dev_priv ); \
|
||||
} else { \
|
||||
mga_do_dma_flush( dev_priv ); \
|
||||
} \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
#include "mga_drv.h"
|
||||
#include "drm.h"
|
||||
|
||||
#include <linux/interrupt.h> /* For task queue support */
|
||||
|
||||
|
||||
/* If you change the functions to set state, PLEASE
|
||||
|
|
@ -69,6 +70,8 @@ static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
|
|||
unsigned int pitch = dev_priv->front_pitch / dev_priv->fb_cpp;
|
||||
DMA_LOCALS;
|
||||
|
||||
return;
|
||||
|
||||
BEGIN_DMA( 2 );
|
||||
|
||||
/* Force reset of DWGCTL on G400 (eliminates clip disable bit).
|
||||
|
|
@ -505,12 +508,9 @@ static int mga_verify_tex_blit( drm_mga_private_t *dev_priv,
|
|||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ================================================================
|
||||
*
|
||||
*/
|
||||
|
||||
static void mga_dma_dispatch_clear( drm_device_t *dev,
|
||||
drm_mga_clear_t *clear )
|
||||
|
|
@ -522,7 +522,10 @@ static void mga_dma_dispatch_clear( drm_device_t *dev,
|
|||
int nbox = sarea_priv->nbox;
|
||||
int i;
|
||||
DMA_LOCALS;
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
DRM_INFO( "%s\n", __FUNCTION__ );
|
||||
|
||||
spin_lock_bh( &dev_priv->prim.lock );
|
||||
DRM_INFO( "spin_lock_bh() in %s\n", __FUNCTION__ );
|
||||
|
||||
for ( i = 0 ; i < nbox ; i++ ) {
|
||||
unsigned int height = pbox[i].y2 - pbox[i].y1;
|
||||
|
|
@ -579,6 +582,9 @@ static void mga_dma_dispatch_clear( drm_device_t *dev,
|
|||
MGA_DWGCTL, ctx->dwgctl );
|
||||
|
||||
ADVANCE_DMA();
|
||||
|
||||
DRM_INFO( "spin_unlock_bh() in %s\n", __FUNCTION__ );
|
||||
spin_unlock_bh( &dev_priv->prim.lock );
|
||||
}
|
||||
|
||||
static void mga_dma_dispatch_swap( drm_device_t *dev )
|
||||
|
|
@ -591,7 +597,10 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
|
|||
u32 pitch = dev_priv->front_pitch / dev_priv->fb_cpp;
|
||||
int i;
|
||||
DMA_LOCALS;
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
DRM_INFO( "%s\n", __FUNCTION__ );
|
||||
|
||||
spin_lock_bh( &dev_priv->prim.lock );
|
||||
DRM_INFO( "spin_lock_bh() in %s\n", __FUNCTION__ );
|
||||
|
||||
BEGIN_DMA( 4 + nbox );
|
||||
|
||||
|
|
@ -627,6 +636,9 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
|
|||
MGA_DWGCTL, ctx->dwgctl );
|
||||
|
||||
ADVANCE_DMA();
|
||||
|
||||
DRM_INFO( "spin_unlock_bh() in %s\n", __FUNCTION__ );
|
||||
spin_unlock_bh( &dev_priv->prim.lock );
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -637,26 +649,26 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
|
|||
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
u32 address = (u32) buf->bus_address;
|
||||
u32 length = (u32) buf->used;
|
||||
int use_agp = PDEA_pagpxfer_enable;
|
||||
int i = 0;
|
||||
DMA_LOCALS;
|
||||
|
||||
DRM_DEBUG( "%s: buf=%d used=%d\n",
|
||||
DRM_INFO( "%s: buf=%d used=%d\n",
|
||||
__FUNCTION__, buf->idx, buf->used );
|
||||
|
||||
spin_lock_bh( &dev_priv->prim.lock );
|
||||
DRM_INFO( "spin_lock_bh() in %s\n", __FUNCTION__ );
|
||||
|
||||
if ( buf->used ) {
|
||||
buf_priv->dispatched = 1;
|
||||
|
||||
MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
|
||||
|
||||
do {
|
||||
#if 0
|
||||
if ( i < sarea_priv->nbox ) {
|
||||
mga_emit_clip_rect( dev_priv,
|
||||
&sarea_priv->boxes[i] );
|
||||
}
|
||||
#endif
|
||||
#if 1
|
||||
|
||||
BEGIN_DMA( 1 );
|
||||
|
||||
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
|
||||
|
|
@ -667,7 +679,6 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
|
|||
MGA_PAGPXFER) );
|
||||
|
||||
ADVANCE_DMA();
|
||||
#endif
|
||||
} while ( ++i < sarea_priv->nbox );
|
||||
}
|
||||
|
||||
|
|
@ -695,6 +706,9 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
|
|||
|
||||
mga_freelist_put( dev, buf );
|
||||
}
|
||||
|
||||
DRM_INFO( "spin_unlock_bh() in %s\n", __FUNCTION__ );
|
||||
spin_unlock_bh( &dev_priv->prim.lock );
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -822,7 +836,6 @@ int mga_dma_clear( struct inode *inode, struct file *filp,
|
|||
*/
|
||||
dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
|
||||
|
||||
MAYBE_FLUSH_DMA();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -845,7 +858,16 @@ int mga_dma_swap( struct inode *inode, struct file *filp,
|
|||
*/
|
||||
dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
|
||||
|
||||
MAYBE_FLUSH_DMA();
|
||||
/* If we're idle, flush the primary DMA stream...
|
||||
*/
|
||||
spin_lock_bh( &dev_priv->prim.lock );
|
||||
DRM_INFO( "spin_lock_bh() in %s\n", __FUNCTION__ );
|
||||
|
||||
FLUSH_DMA();
|
||||
|
||||
DRM_INFO( "spin_unlock_bh() in %s\n", __FUNCTION__ );
|
||||
spin_unlock_bh( &dev_priv->prim.lock );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -892,7 +914,6 @@ int mga_dma_vertex( struct inode *inode, struct file *filp,
|
|||
|
||||
mga_dma_dispatch_vertex( dev, buf );
|
||||
|
||||
MAYBE_FLUSH_DMA();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue