mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-07 23:58:04 +02:00
Don't really use the status page, keep the ring write pointer ourselves.
'book/double' will sit there and happily spin away, which kind of
implies the DMA handling works well now. Other apps still causing
lockups, most likely due to the fact I haven't fixed the rest of the
code yet.
This commit is contained in:
Gareth Hughes
parent
c79ebf19ee
commit
b6f4c2f7bf
3 changed files with 81 additions and 115 deletions
150
linux/mga_dma.c
150
linux/mga_dma.c
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@ -1087,7 +1087,7 @@ int mga_do_dma_reset( drm_mga_private_t *dev_priv )
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/* The primary DMA stream should look like new right about now.
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*/
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*dev_priv->prim.head = dev_priv->primary->offset;
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dev_priv->prim.head = 0;
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dev_priv->prim.tail = 0;
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dev_priv->prim.wrap = 0;
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dev_priv->prim.space = dev_priv->prim.size - MGA_DMA_SOFTRAP_SIZE;
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@ -1124,10 +1124,12 @@ int mga_do_engine_reset( drm_mga_private_t *dev_priv )
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* 3D clients should probably die after calling this. The X
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* server should reset the engine state to known values.
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*/
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#if 0
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MGA_WRITE( MGA_PRIMPTR,
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virt_to_bus((void *)dev_priv->prim.status_page) |
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MGA_PRIMPTREN0 |
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MGA_PRIMPTREN1 );
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#endif
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MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR );
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MGA_WRITE( MGA_IEN, MGA_SOFTRAPIEN );
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@ -1153,37 +1155,25 @@ static inline void mga_do_dma( drm_mga_private_t *dev_priv,
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u32 head, u32 tail )
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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DRM_INFO( "%s:\n", __FUNCTION__ );
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DRM_DEBUG( "%s:\n", __FUNCTION__ );
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/* Only flush the primary DMA stream if there are new commands.
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*/
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if ( head == tail ) {
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PRINT_DMA_STATE( dev_priv );
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DRM_INFO( " bailing out...\n" );
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DRM_DEBUG( " bailing out...\n" );
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clear_bit( 0, &dev_priv->dma_flag );
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return;
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}
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if ( 1 ) {
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u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
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if ( status != MGA_ENDPRDMASTS ) {
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DRM_ERROR( "DMA engine not idle!\n" );
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status = *((u32 *)0x00000000);
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}
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if ( MGA_READ( MGA_STATUS ) & MGA_SOFTRAPEN ) {
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DRM_ERROR( "DMA engine SOFTRAP interrupt pending!\n" );
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status = *((u32 *)0x00000000);
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}
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}
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DRM_INFO( " head = 0x%08x 0x%04x\n",
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DRM_DEBUG( " head = 0x%08x 0x%04x\n",
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head, head - dev_priv->primary->offset );
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DRM_INFO( " tail = 0x%08x 0x%04x\n",
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DRM_DEBUG( " tail = 0x%08x 0x%04x\n",
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tail, tail - dev_priv->primary->offset );
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if ( tail <= head ) {
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u32 tmp;
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u32 tmp, *fuck = 0x12345678;
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DRM_ERROR( "FUCK ME DEAD\n" );
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tmp = *((u32 *)0x00000000);
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tmp = *fuck;
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}
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clear_bit( MGA_DMA_IDLE, &primary->state );
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@ -1192,10 +1182,10 @@ static inline void mga_do_dma( drm_mga_private_t *dev_priv,
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MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
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MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
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DRM_INFO( "%s: done.\n", __FUNCTION__ );
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mga_do_wait_for_idle( dev_priv );
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DRM_INFO( "%s: idle.\n", __FUNCTION__ );
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clear_bit( 0, &dev_priv->dma_flag );
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DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
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}
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void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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@ -1203,7 +1193,7 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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u32 head, tail;
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DMA_LOCALS;
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DRM_INFO( "%s\n", __FUNCTION__ );
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DRM_DEBUG( "%s:\n", __FUNCTION__ );
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if ( test_and_set_bit( 0, &dev_priv->dma_flag ) ) {
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DRM_ERROR( "wtf???\n" );
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@ -1220,8 +1210,9 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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/* Only flush the primary DMA stream if there are new commands.
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*/
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if ( primary->tail == primary->last_flush ) {
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DRM_INFO( " bailing out...\n" );
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goto cleanup;
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DRM_DEBUG( " bailing out...\n" );
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clear_bit( 0, &dev_priv->dma_flag );
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return;
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}
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/* Writing the SOFTRAP register will cause an interrupt. We use
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@ -1236,40 +1227,22 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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ADVANCE_DMA();
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/* Reset the PRIMADDRESS pointer if we wrapped after the last
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* batch of commands.
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*/
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if ( test_bit( MGA_DMA_WRAP, &primary->state ) ) {
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*primary->head = dev_priv->primary->offset;
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primary->space = (primary->size - primary->tail -
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MGA_DMA_SOFTRAP_SIZE);
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DRM_INFO( " clearing wrap: tail=0x%04x space=0x%x\n",
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primary->tail, primary->space );
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clear_bit( MGA_DMA_WRAP, &primary->state );
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}
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/* The primary DMA stream must be idle here, so we can safely
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* cache this value. Prevents doing multiple uncached reads
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* from the DMA status page.
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*/
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head = *primary->head;
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tail = primary->tail + dev_priv->primary->offset;
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primary->space = primary->size - primary->tail - MGA_DMA_SOFTRAP_SIZE;
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primary->last_flush = primary->tail;
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head = primary->head + dev_priv->primary->offset;
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tail = primary->tail + dev_priv->primary->offset;
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/* Kick off the DMA transfer.
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*/
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mga_do_dma( dev_priv, head, tail );
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cleanup:
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clear_bit( 0, &dev_priv->dma_flag );
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}
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void mga_do_dma_wrap( drm_mga_private_t *dev_priv )
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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u32 head, tail;
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DRM_INFO( "%s\n", __FUNCTION__ );
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DRM_DEBUG( "%s:\n", __FUNCTION__ );
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if ( test_and_set_bit( 0, &dev_priv->dma_flag ) ) {
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DRM_ERROR( "wtf???\n" );
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@ -1279,15 +1252,12 @@ void mga_do_dma_wrap( drm_mga_private_t *dev_priv )
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/* Only wrap the primary DMA stream if we have to.
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*/
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if ( !primary->wrap ) {
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DRM_INFO( " bailing out...\n" );
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goto cleanup;
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DRM_DEBUG( " bailing out...\n" );
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clear_bit( 0, &dev_priv->dma_flag );
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return;
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}
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/* The primary DMA stream must be idle here, so we can safely
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* cache this value. Prevents doing multiple uncached reads
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* from the DMA status page.
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*/
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head = *primary->head;
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head = primary->head + dev_priv->primary->offset;
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/* Wrap the primary DMA stream. We use primary->wrap to
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* determine when the comamnds have wrapped around, and
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@ -1298,15 +1268,9 @@ void mga_do_dma_wrap( drm_mga_private_t *dev_priv )
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tail = primary->wrap + dev_priv->primary->offset;
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primary->wrap = 0;
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DRM_INFO( " setting wrap...\n" );
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set_bit( MGA_DMA_WRAP, &primary->state );
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/* Kick off the DMA transfer.
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*/
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mga_do_dma( dev_priv, head, tail );
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cleanup:
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clear_bit( 0, &dev_priv->dma_flag );
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}
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void mga_dma_wrap_or_wait( drm_mga_private_t *dev_priv, int n )
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@ -1333,8 +1297,10 @@ void mga_dma_wrap_or_wait( drm_mga_private_t *dev_priv, int n )
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primary->tail = 0;
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primary->last_flush = 0;
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while ( mga_do_wait_for_idle( dev_priv ) < 0 )
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;
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primary->space = primary->head - MGA_DMA_SOFTRAP_SIZE;
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DRM_INFO( " wrap=0x%04x head=0x%04x space=0x%x\n",
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primary->wrap, primary->head, primary->space );
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/* Kick off the last chunk of commands immediately if
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* the primary DMA stream is idle. This makes wrapping
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@ -1343,17 +1309,6 @@ void mga_dma_wrap_or_wait( drm_mga_private_t *dev_priv, int n )
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if ( MGA_DMA_IS_IDLE( dev_priv ) ) {
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mga_do_dma_wrap( dev_priv );
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}
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{
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u32 head = *primary->head;
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primary->space = (head - dev_priv->primary->offset -
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MGA_DMA_SOFTRAP_SIZE);
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DRM_INFO( " head=0x%08x 0x%04x space=0x%x\n",
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head, head - dev_priv->primary->offset,
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primary->space );
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}
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} else {
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/* FIXME: This is terribly broken...
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*/
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@ -1363,8 +1318,7 @@ void mga_dma_wrap_or_wait( drm_mga_private_t *dev_priv, int n )
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mga_do_dma_flush( dev_priv );
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primary->space = (*primary->head - primary->tail -
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dev_priv->primary->offset);
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primary->space = (primary->head - primary->tail);
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}
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}
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@ -1375,7 +1329,7 @@ void mga_update_primary_snapshot( drm_mga_private_t *dev_priv )
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if ( !primary->wrap ) {
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primary->space = primary->size - primary->tail;
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} else {
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primary->space = (*primary->head - primary->tail -
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primary->space = (primary->head - primary->tail -
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dev_priv->primary->offset);
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}
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@ -1418,7 +1372,7 @@ int mga_dma_schedule( drm_device_t *dev, int locked )
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{
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drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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DRM_INFO( "%s: prim=0x%x low=0x%x\n",
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DRM_DEBUG( "%s: prim=0x%x low=0x%x\n",
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__FUNCTION__,
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dev_priv->prim.tail - dev_priv->prim.last_flush,
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dev_priv->prim.low_mark);
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@ -1430,24 +1384,23 @@ int mga_dma_schedule( drm_device_t *dev, int locked )
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set_bit( MGA_DMA_IDLE, &primary->state );
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primary->head = primary->last_flush;
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if ( dev_priv->prim.wrap ) {
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DRM_INFO( " wrapping primary DMA...\n" );
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DRM_DEBUG( " wrapping primary DMA...\n" );
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mga_do_dma_wrap( dev_priv );
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} else if ( test_bit( MGA_DMA_FLUSH, &dev_priv->prim.state ) ) {
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DRM_INFO( " forcing primary DMA...\n" );
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DRM_DEBUG( " forcing primary DMA...\n" );
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mga_do_dma_flush( dev_priv );
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} else if ( dev_priv->prim.tail - dev_priv->prim.last_flush >=
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dev_priv->prim.low_mark ) {
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DRM_INFO( " flushing primary DMA...\n" );
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DRM_DEBUG( " flushing primary DMA...\n" );
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mga_do_dma_flush( dev_priv );
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} else {
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DRM_INFO( " going idle...\n" );
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DRM_DEBUG( " going idle...\n" );
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}
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#if 0
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PRINT_DMA_STATE( dev_priv );
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#endif
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DRM_INFO( "%s: done.\n", __FUNCTION__ );
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DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
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clear_bit( 0, &dev_priv->interrupt_flag );
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return 0;
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@ -1719,17 +1672,19 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
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/* Init the DMA status pointer.
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*/
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#if 0
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MGA_WRITE( MGA_PRIMPTR,
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virt_to_bus((void *)dev_priv->prim.status_page) |
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MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
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0 /*MGA_PRIMPTREN1*/ ); /* DWGSYNC */
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#endif
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dev_priv->prim.start = (u8 *)dev_priv->primary->handle;
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dev_priv->prim.end = ((u8 *)dev_priv->primary->handle
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+ dev_priv->primary->size);
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dev_priv->prim.size = dev_priv->primary->size;
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dev_priv->prim.head = (volatile u32 *) dev_priv->prim.status;
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dev_priv->prim.head = 0;
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dev_priv->prim.tail = 0;
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dev_priv->prim.wrap = 0;
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dev_priv->prim.space = dev_priv->prim.size - MGA_DMA_SOFTRAP_SIZE;
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@ -1741,12 +1696,6 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
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set_bit( MGA_DMA_IDLE, &dev_priv->prim.state );
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/* We use the status copy of PRIMADDRESS as the value we write
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* to the hardware, so initialize it to the beginning of primary
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* DMA space here.
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*/
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*dev_priv->prim.head = dev_priv->primary->offset;
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dev_priv->sarea_priv->last_dispatch = 0;
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dev_priv->prim.status[1] = 0;
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@ -1953,10 +1902,11 @@ if ( 0 ) {
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DRM_INFO( " end = %p\n", dev_priv->prim.end );
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DRM_INFO( "space = %d \n", dev_priv->prim.space );
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#if 0
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/* Let's lock the board and then recover from it. Isn't it
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* nice to be able to do so?
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*/
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*dev_priv->prim.head += 4096;
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dev_priv->prim.head += 4096;
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dev_priv->prim.tail = 128;
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mga_do_dma_flush( dev_priv );
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@ -1965,12 +1915,13 @@ if ( 0 ) {
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if ( ret < 0 ) {
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mga_do_engine_reset( dev_priv );
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}
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#endif
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/* You'll notice that this does not fail. Cool, eh?
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*/
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mga_do_wait_for_idle( dev_priv );
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for ( i = 0 ; i < 16 * 1024 ; i++ ) {
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for ( i = 0 ; i < 256 * 1024 ; i++ ) {
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DMA_LOCALS;
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BEGIN_DMA( 8 );
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@ -2027,19 +1978,22 @@ if ( 0 ) {
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mga_do_dma_flush( dev_priv );
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#if 0
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if ( mga_do_wait_for_idle( dev_priv ) < 0 )
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return -EINVAL;
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#endif
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}
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}
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/* Flush the primary DMA stream.
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*/
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mga_do_wait_for_idle( dev_priv );
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DRM_INFO( "*** forcing final flush now ***\n" );
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mga_do_dma_flush( dev_priv );
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mga_do_wait_for_idle( dev_priv );
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DRM_INFO( "head = 0x%08x\n", dev_priv->prim.status[0] );
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DRM_INFO( "sync = 0x%08x\n", dev_priv->prim.status[1] );
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DRM_DEBUG( "head = 0x%08x\n", dev_priv->prim.status[0] );
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DRM_DEBUG( "sync = 0x%08x\n", dev_priv->prim.status[1] );
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DRM_INFO( "\n" );
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DRM_INFO( "space = 0x%x / 0x%x\n",
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dev_priv->prim.space,
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@ -60,7 +60,7 @@ typedef struct drm_mga_primary_buffer {
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u8 *end;
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int size;
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volatile u32 *head;
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u32 head;
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u32 tail;
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u32 wrap;
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int space;
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@ -317,8 +317,7 @@ static inline void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
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MGA_DWGCTL, MGA_DWGCTL_FLUSH );
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DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001,
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/*MGA_DWGSYNC, 0x00007000,*/
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MGA_DMAPAD, 0x00000000,
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MGA_DWGSYNC, 0x00007000,
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MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
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MGA_LEN + MGA_EXEC, 0x00000000 );
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@ -525,7 +524,6 @@ static void mga_dma_dispatch_clear( drm_device_t *dev,
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DMA_LOCALS;
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DRM_DEBUG( "%s\n", __FUNCTION__ );
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#if 1
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for ( i = 0 ; i < nbox ; i++ ) {
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unsigned int height = pbox[i].y2 - pbox[i].y1;
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@ -572,7 +570,15 @@ static void mga_dma_dispatch_clear( drm_device_t *dev,
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ADVANCE_DMA();
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}
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#endif
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BEGIN_DMA( 1 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_PLNWT, ctx->plnwt,
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MGA_DWGCTL, ctx->dwgctl );
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ADVANCE_DMA();
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}
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static void mga_dma_dispatch_swap( drm_device_t *dev )
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||||
|
|
@ -587,12 +593,16 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
|
|||
DMA_LOCALS;
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
#if 1
|
||||
BEGIN_DMA( 2 + nbox );
|
||||
BEGIN_DMA( 4 + nbox );
|
||||
|
||||
DMA_BLOCK( MGA_MACCESS, dev_priv->maccess,
|
||||
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
|
||||
MGA_DMAPAD, 0x00000000,
|
||||
MGA_DWGSYNC, 0x00007100,
|
||||
MGA_DWGSYNC, 0x00007000 );
|
||||
|
||||
DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset,
|
||||
MGA_MACCESS, dev_priv->maccess,
|
||||
MGA_SRCORG, dev_priv->back_offset,
|
||||
MGA_DSTORG, dev_priv->front_offset,
|
||||
MGA_AR5, pitch );
|
||||
|
||||
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
|
||||
|
|
@ -611,8 +621,12 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
|
|||
(pbox[i].y1 << 16) | h );
|
||||
}
|
||||
|
||||
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
|
||||
MGA_PLNWT, ctx->plnwt,
|
||||
MGA_SRCORG, dev_priv->front_offset,
|
||||
MGA_DWGCTL, ctx->dwgctl );
|
||||
|
||||
ADVANCE_DMA();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -632,15 +646,17 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
|
|||
|
||||
if ( buf->used ) {
|
||||
buf_priv->dispatched = 1;
|
||||
#if 1
|
||||
|
||||
MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
|
||||
|
||||
do {
|
||||
#if 0
|
||||
if ( i < sarea_priv->nbox ) {
|
||||
mga_emit_clip_rect( dev_priv,
|
||||
&sarea_priv->boxes[i] );
|
||||
}
|
||||
|
||||
#endif
|
||||
#if 1
|
||||
BEGIN_DMA( 1 );
|
||||
|
||||
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
|
||||
|
|
@ -651,8 +667,8 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
|
|||
MGA_PAGPXFER) );
|
||||
|
||||
ADVANCE_DMA();
|
||||
} while ( ++i < sarea_priv->nbox );
|
||||
#endif
|
||||
} while ( ++i < sarea_priv->nbox );
|
||||
}
|
||||
|
||||
if ( buf_priv->discard ) {
|
||||
|
|
@ -830,8 +846,6 @@ int mga_dma_swap( struct inode *inode, struct file *filp,
|
|||
dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
|
||||
|
||||
MAYBE_FLUSH_DMA();
|
||||
|
||||
mga_do_wait_for_idle( dev_priv );
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -879,8 +893,6 @@ int mga_dma_vertex( struct inode *inode, struct file *filp,
|
|||
mga_dma_dispatch_vertex( dev, buf );
|
||||
|
||||
MAYBE_FLUSH_DMA();
|
||||
|
||||
mga_do_wait_for_idle( dev_priv );
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue