mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-14 05:18:04 +02:00
Finally... No-IRQ DMA works as expected (and doesn't suffer from the odd
random lockup like the old scheme).
This commit is contained in:
Gareth Hughes
parent
6038ace5dc
commit
ac53737146
5 changed files with 45 additions and 469 deletions
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@ -55,18 +55,11 @@
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[DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \
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[DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_dma_iload, 1, 0 },
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#define __HAVE_DMA_IRQ 1
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#define __HAVE_COUNTERS 3
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#define __HAVE_COUNTER6 _DRM_STAT_IRQ
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#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
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#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY
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#if 0
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#define __HAVE_DMA_QUEUE 1
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#define __HAVE_DMA_SCHEDULE 1
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#endif
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#define __HAVE_DMA_QUIESCENT 1
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#define DRIVER_DMA_QUIESCENT() \
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do { \
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369
linux/mga_dma.c
369
linux/mga_dma.c
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@ -199,21 +199,15 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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u32 head, tail;
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unsigned long flags;
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DMA_LOCALS;
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DRM_DEBUG( "%s:\n", __FUNCTION__ );
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if ( primary->tail == primary->last_flush + DMA_BLOCK_SIZE ) {
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if ( primary->tail == primary->last_flush ) {
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DRM_DEBUG( " bailing out...\n" );
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return;
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}
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spin_lock_irqsave( &primary->flush_lock, flags );
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tail = primary->tail + dev_priv->primary->offset;
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primary->last_flush = primary->tail;
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spin_unlock_irqrestore( &primary->flush_lock, flags );
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BEGIN_DMA( 1 );
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@ -224,6 +218,8 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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ADVANCE_DMA();
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primary->last_flush = primary->tail;
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head = *primary->head;
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if ( head <= tail ) {
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@ -232,19 +228,9 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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primary->space = head - tail;
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}
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if ( test_bit( 0, &primary->wrap_flag ) ) {
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DRM_DEBUG( "%s: pending wrap...\n", __FUNCTION__ );
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spin_unlock_irqrestore( &primary->flush_lock, flags );
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return;
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}
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#if 0
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DRM_INFO( " head = 0x%06lx\n",
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head - dev_priv->primary->offset );
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DRM_INFO( " tail = 0x%06lx\n",
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tail - dev_priv->primary->offset );
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DRM_INFO( " space = 0x%06x\n", primary->space );
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#endif
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DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset );
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DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset );
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DRM_DEBUG( " space = 0x%06x\n", primary->space );
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mga_flush_write_combine();
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MGA_WRITE( MGA_PRIMEND, tail | MGA_PRIMNOSTART | MGA_PAGPXFER );
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@ -252,27 +238,27 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
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DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
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}
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void mga_do_dma_wrap( drm_mga_private_t *dev_priv )
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void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
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{
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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u32 head, tail;
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unsigned long flags;
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DMA_LOCALS;
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DRM_DEBUG( "%s:\n", __FUNCTION__ );
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spin_lock_irqsave( &primary->flush_lock, flags );
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BEGIN_DMA_WRAP();
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_SOFTRAP, 0x00000000 );
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MGA_DWGSYNC, 0x12345678 );
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ADVANCE_DMA();
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tail = primary->tail + dev_priv->primary->offset;
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primary->tail = 0;
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primary->last_flush = 0;
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primary->last_wrap++;
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head = *primary->head;
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@ -282,93 +268,33 @@ void mga_do_dma_wrap( drm_mga_private_t *dev_priv )
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primary->space = head - dev_priv->primary->offset;
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}
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primary->last_flush = 0;
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primary->last_wrap++;
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set_bit( 0, &primary->wrap_flag );
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if ( 0 ) {
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DRM_INFO( "%s:\n", __FUNCTION__ );
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DRM_INFO( " head = 0x%06lx\n",
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head - dev_priv->primary->offset );
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DRM_INFO( " tail = 0x%06x\n", primary->tail );
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DRM_INFO( " wrap = %d\n", primary->last_wrap );
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DRM_INFO( " space = 0x%06x\n", primary->space );
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}
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DRM_DEBUG( " head = 0x%06lx\n",
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head - dev_priv->primary->offset );
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DRM_DEBUG( " tail = 0x%06x\n", primary->tail );
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DRM_DEBUG( " wrap = %d\n", primary->last_wrap );
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DRM_DEBUG( " space = 0x%06x\n", primary->space );
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mga_flush_write_combine();
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MGA_WRITE( MGA_PRIMEND, tail | MGA_PRIMNOSTART | MGA_PAGPXFER );
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spin_unlock_irqrestore( &primary->flush_lock, flags );
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DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
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mga_do_wait_for_idle( dev_priv );
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}
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/* ================================================================
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* DMA interrupt handling
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*/
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static void mga_dma_service( int irq, void *device, struct pt_regs *regs )
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void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
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{
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drm_device_t *dev = (drm_device_t *)device;
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drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
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u32 head = dev_priv->primary->offset;
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u32 flush;
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DRM_DEBUG( "%s:\n", __FUNCTION__ );
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/* Verify the interrupt we're servicing is actually the one we
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* want to service.
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*/
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if ( (MGA_READ( MGA_STATUS ) & MGA_SOFTRAPEN) != MGA_SOFTRAPEN )
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return;
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atomic_inc( &dev->counts[_DRM_STAT_IRQ] );
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spin_lock( &primary->flush_lock );
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MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR );
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flush = primary->last_flush + dev_priv->primary->offset;
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sarea_priv->last_wrap++;
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clear_bit( 0, &primary->wrap_flag );
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#if 0
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DRM_INFO( " *** wrap interrupt:\n" );
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DRM_INFO( " head = 0x%06lx\n",
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head - dev_priv->primary->offset );
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DRM_INFO( " flush = 0x%06lx\n", primary->last_flush );
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DRM_INFO( " tail = 0x%06lx %s\n",
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primary->tail,
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primary->tail != primary->last_flush + DMA_BLOCK_SIZE
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? "***" : "" );
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DRM_INFO( " wrap = %d\n", sarea_priv->last_wrap );
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#endif
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*primary->head = head;
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mga_flush_write_combine();
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MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
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if ( primary->last_flush > 0 ) {
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MGA_WRITE( MGA_PRIMEND, flush | MGA_PAGPXFER );
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}
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spin_unlock( &primary->flush_lock );
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}
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static int mga_dma_task_queue( void *dev )
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{
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drm_mga_private_t *dev_priv = ((drm_device_t *)dev)->dev_private;
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drm_mga_primary_buffer_t *primary = &dev_priv->prim;
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spin_lock( &primary->list_lock );
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mga_do_freelist_wrap( dev );
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spin_unlock( &primary->list_lock );
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return 0;
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DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
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}
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@ -554,30 +480,6 @@ static int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
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return 0;
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}
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/* The list spinlock must have been acquired before this can be called...
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*/
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void mga_do_freelist_wrap( drm_device_t *dev )
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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drm_mga_freelist_t *entry;
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u32 head = *dev_priv->prim.head;
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DRM_INFO( "%s:\n", __FUNCTION__ );
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#if 0
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DRM_DEBUG( " before...\n" );
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mga_freelist_print( dev );
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#endif
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for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) {
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SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
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}
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#if 0
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DRM_DEBUG( " after...\n" );
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mga_freelist_print( dev );
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#endif
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}
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/* ================================================================
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* DMA initialization, cleanup
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@ -677,9 +579,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
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dev_priv->prim.last_flush = 0;
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dev_priv->prim.last_wrap = 0;
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clear_bit( 0, &dev_priv->prim.wrap_flag );
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dev_priv->prim.high_mark = 0;
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dev_priv->prim.high_mark = 128 * DMA_BLOCK_SIZE;
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spin_lock_init( &dev_priv->prim.flush_lock );
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spin_lock_init( &dev_priv->prim.list_lock );
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@ -707,20 +608,10 @@ int mga_do_cleanup_dma( drm_device_t *dev )
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if ( dev->dev_private ) {
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drm_mga_private_t *dev_priv = dev->dev_private;
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#if 0
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if ( dev_priv->prim.status_page ) {
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mga_free_page( dev_priv->prim.status_page );
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}
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#endif
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DO_IOREMAPFREE( dev_priv->warp );
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DO_IOREMAPFREE( dev_priv->primary );
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DO_IOREMAPFREE( dev_priv->buffers );
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/* Make sure we catch this here...
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*/
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if ( dev->irq ) mga_irq_uninstall( dev );
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if ( dev_priv->head != NULL ) {
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mga_freelist_cleanup( dev );
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}
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@ -754,7 +645,6 @@ int mga_dma_init( struct inode *inode, struct file *filp,
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}
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/* ================================================================
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* Primary DMA stream management
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*/
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@ -802,223 +692,6 @@ int mga_dma_reset( struct inode *inode, struct file *filp,
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}
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/* ================================================================
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* IRQ management
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*/
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int mga_irq_install( drm_device_t *dev, int irq )
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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int ret;
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if ( !irq ) return -EINVAL;
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down( &dev->struct_sem );
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if ( dev->irq ) {
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up( &dev->struct_sem );
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return -EBUSY;
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}
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dev->irq = irq;
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up( &dev->struct_sem );
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DRM_DEBUG( "install irq handler %d\n", irq );
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dev->context_flag = 0;
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dev->interrupt_flag = 0;
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dev->dma_flag = 0;
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dev->dma->next_buffer = NULL;
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dev->dma->next_queue = NULL;
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dev->dma->this_buffer = NULL;
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#if 0
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INIT_LIST_HEAD(&dev->tq.list);
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dev->tq.sync = 0;
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dev->tq.routine = (void (*)(void *))mga_dma_task_queue;
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dev->tq.data = dev;
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#endif
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/* Before installing handler
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*/
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MGA_WRITE( MGA_IEN, 0 );
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/* Install handler
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*/
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ret = request_irq( dev->irq,
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mga_dma_service,
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SA_SHIRQ,
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dev->devname,
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dev );
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if ( ret ) {
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down( &dev->struct_sem );
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dev->irq = 0;
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up( &dev->struct_sem );
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return ret;
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}
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/* After installing handler
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*/
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MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR );
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MGA_WRITE( MGA_IEN, MGA_SOFTRAPIEN );
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if ( 0 ) {
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int i;
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int ret;
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DRM_INFO( "start = %p\n", dev_priv->prim.start );
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DRM_INFO( " end = %p\n", dev_priv->prim.end );
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DRM_INFO( "space = %d \n", dev_priv->prim.space );
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#if 0
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/* Let's lock the board and then recover from it. Isn't it
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* nice to be able to do so?
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*/
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dev_priv->prim.head += 4096;
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dev_priv->prim.tail = 128;
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mga_do_dma_flush( dev_priv );
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ret = mga_do_wait_for_idle( dev_priv );
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if ( ret < 0 ) {
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mga_do_engine_reset( dev_priv );
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}
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#endif
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/* You'll notice that this does not fail. Cool, eh?
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*/
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mga_do_wait_for_idle( dev_priv );
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for ( i = 0 ; i < 256 ; i++ ) {
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DMA_LOCALS;
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BEGIN_DMA( 8 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000 );
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DMA_BLOCK( MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DMAPAD, 0x00000000,
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MGA_DWGSYNC, 0x12345678 );
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ADVANCE_DMA();
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mga_do_dma_flush( dev_priv );
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udelay( 5 );
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DRM_INFO( "\n" );
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DRM_INFO( "head = 0x%08lx 0x%06lx\n",
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(unsigned long)dev_priv->prim.status[0],
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dev_priv->prim.status[0] -
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dev_priv->primary->offset );
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DRM_INFO( "sync = 0x%08x\n", dev_priv->prim.status[1] );
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DRM_INFO( "\n" );
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}
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udelay( 10 );
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ret = 0;
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if ( mga_do_wait_for_idle( dev_priv ) < 0 )
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ret = -EINVAL;
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DRM_INFO( "head = 0x%08lx 0x%06lx\n",
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(unsigned long)dev_priv->prim.status[0],
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dev_priv->prim.status[0] - dev_priv->primary->offset );
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DRM_INFO( "sync = 0x%08x\n", dev_priv->prim.status[1] );
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DRM_INFO( "\n" );
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DRM_INFO( "space = 0x%x / 0x%x\n",
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dev_priv->prim.space, dev_priv->prim.size );
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DRM_INFO( "\n" );
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DRM_INFO( " irqs = %d\n", atomic_read( &dev->counts[_DRM_STAT_IRQ] ) );
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return ret;
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}
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return 0;
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}
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int mga_irq_uninstall( drm_device_t *dev )
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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int irq;
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|
||||
down( &dev->struct_sem );
|
||||
irq = dev->irq;
|
||||
dev->irq = 0;
|
||||
up( &dev->struct_sem );
|
||||
|
||||
if ( !irq ) return -EINVAL;
|
||||
|
||||
DRM_DEBUG( "remove irq handler %d\n", irq );
|
||||
|
||||
MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR );
|
||||
MGA_WRITE( MGA_IEN, 0 );
|
||||
|
||||
free_irq( irq, dev );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mga_control( struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg )
|
||||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
drm_control_t ctl;
|
||||
|
||||
if ( copy_from_user( &ctl, (drm_control_t *)arg, sizeof(ctl) ) )
|
||||
return -EFAULT;
|
||||
|
||||
switch ( ctl.func ) {
|
||||
case DRM_INST_HANDLER:
|
||||
return mga_irq_install( dev, ctl.irq );
|
||||
case DRM_UNINST_HANDLER:
|
||||
return mga_irq_uninstall( dev );
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* DMA buffer management
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -55,18 +55,11 @@
|
|||
[DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_dma_iload, 1, 0 },
|
||||
|
||||
#define __HAVE_DMA_IRQ 1
|
||||
|
||||
#define __HAVE_COUNTERS 3
|
||||
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
|
||||
#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
|
||||
#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY
|
||||
|
||||
#if 0
|
||||
#define __HAVE_DMA_QUEUE 1
|
||||
#define __HAVE_DMA_SCHEDULE 1
|
||||
#endif
|
||||
|
||||
#define __HAVE_DMA_QUIESCENT 1
|
||||
#define DRIVER_DMA_QUIESCENT() \
|
||||
do { \
|
||||
|
|
|
|||
121
linux/mga_drv.h
121
linux/mga_drv.h
|
|
@ -68,11 +68,9 @@ typedef struct drm_mga_primary_buffer {
|
|||
|
||||
u32 last_flush;
|
||||
u32 last_wrap;
|
||||
__volatile__ long wrap_flag;
|
||||
|
||||
u32 high_mark;
|
||||
|
||||
spinlock_t flush_lock;
|
||||
spinlock_t list_lock;
|
||||
} drm_mga_primary_buffer_t;
|
||||
|
||||
|
|
@ -164,7 +162,8 @@ extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
|
|||
extern int mga_do_cleanup_dma( drm_device_t *dev );
|
||||
|
||||
extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
|
||||
extern void mga_do_dma_wrap( drm_mga_private_t *dev_priv );
|
||||
extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
|
||||
extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
|
||||
|
||||
extern int mga_irq_uninstall( drm_device_t *dev );
|
||||
|
||||
|
|
@ -232,6 +231,16 @@ do { \
|
|||
} \
|
||||
} while (0)
|
||||
|
||||
#define WRAP_TEST_WITH_RETURN( dev_priv ) \
|
||||
do { \
|
||||
if ( dev_priv->sarea_priv->last_wrap < \
|
||||
dev_priv->prim.last_wrap ) { \
|
||||
if ( mga_do_wait_for_idle( dev_priv ) < 0 ) \
|
||||
return -EBUSY; \
|
||||
mga_do_dma_wrap_end( dev_priv ); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* Primary DMA command stream
|
||||
|
|
@ -253,7 +262,6 @@ do { \
|
|||
} \
|
||||
if ( dev_priv->prim.space < (int)((n) * DMA_BLOCK_SIZE + \
|
||||
MGA_DMA_SOFTRAP_SIZE) ) { \
|
||||
mga_do_dma_wrap( dev_priv ); \
|
||||
} \
|
||||
prim = dev_priv->prim.start; \
|
||||
write = dev_priv->prim.tail; \
|
||||
|
|
@ -278,19 +286,14 @@ do { \
|
|||
} \
|
||||
} while (0)
|
||||
|
||||
#if 0
|
||||
#define FLUSH_DMA() \
|
||||
do { \
|
||||
if ( dev_priv->prim.space < (int)(128 * DMA_BLOCK_SIZE + \
|
||||
MGA_DMA_SOFTRAP_SIZE) ) { \
|
||||
mga_do_dma_wrap( dev_priv ); \
|
||||
if ( dev_priv->prim.space < dev_priv->prim.high_mark ) { \
|
||||
mga_do_dma_wrap_start( dev_priv ); \
|
||||
} else { \
|
||||
mga_do_dma_flush( dev_priv ); \
|
||||
} \
|
||||
} while (0)
|
||||
#else
|
||||
#define FLUSH_DMA() mga_do_dma_flush( dev_priv );
|
||||
#endif
|
||||
|
||||
/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
|
||||
*/
|
||||
|
|
@ -625,100 +628,4 @@ do { \
|
|||
MGA_BLTMOD_BFCOL | \
|
||||
MGA_CLIPDIS)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define MGA_CLEAR_CMD (DC_opcod_trap | DC_arzero_enable | \
|
||||
DC_sgnzero_enable | DC_shftzero_enable | \
|
||||
(0xC << DC_bop_SHIFT) | DC_clipdis_enable | \
|
||||
DC_solid_enable | DC_transc_enable)
|
||||
|
||||
|
||||
#define MGA_COPY_CMD (DC_opcod_bitblt | DC_atype_rpl | DC_linear_xy | \
|
||||
DC_solid_disable | DC_arzero_disable | \
|
||||
DC_sgnzero_enable | DC_shftzero_enable | \
|
||||
(0xC << DC_bop_SHIFT) | DC_bltmod_bfcol | \
|
||||
DC_pattern_disable | DC_transc_disable | \
|
||||
DC_clipdis_enable) \
|
||||
|
||||
#define MGA_FLUSH_CMD (DC_opcod_texture_trap | (0xF << DC_trans_SHIFT) |\
|
||||
DC_arzero_enable | DC_sgnzero_enable | \
|
||||
DC_atype_i)
|
||||
|
||||
|
||||
#define PDEA_pagpxfer_enable 0x2
|
||||
|
||||
#define WIA_wmode_suspend 0x0
|
||||
#define WIA_wmode_start 0x3
|
||||
#define WIA_wagp_agp 0x4
|
||||
|
||||
#define DC_opcod_line_open 0x0
|
||||
#define DC_opcod_autoline_open 0x1
|
||||
#define DC_opcod_line_close 0x2
|
||||
#define DC_opcod_autoline_close 0x3
|
||||
#define DC_opcod_trap 0x4
|
||||
#define DC_opcod_texture_trap 0x6
|
||||
#define DC_opcod_bitblt 0x8
|
||||
#define DC_opcod_iload 0x9
|
||||
#define DC_atype_rpl 0x0
|
||||
#define DC_atype_rstr 0x10
|
||||
#define DC_atype_zi 0x30
|
||||
#define DC_atype_blk 0x40
|
||||
#define DC_atype_i 0x70
|
||||
#define DC_linear_xy 0x0
|
||||
#define DC_linear_linear 0x80
|
||||
#define DC_zmode_nozcmp 0x0
|
||||
#define DC_zmode_ze 0x200
|
||||
#define DC_zmode_zne 0x300
|
||||
#define DC_zmode_zlt 0x400
|
||||
#define DC_zmode_zlte 0x500
|
||||
#define DC_zmode_zgt 0x600
|
||||
#define DC_zmode_zgte 0x700
|
||||
#define DC_solid_disable 0x0
|
||||
#define DC_solid_enable 0x800
|
||||
#define DC_arzero_disable 0x0
|
||||
#define DC_arzero_enable 0x1000
|
||||
#define DC_sgnzero_disable 0x0
|
||||
#define DC_sgnzero_enable 0x2000
|
||||
#define DC_shftzero_disable 0x0
|
||||
#define DC_shftzero_enable 0x4000
|
||||
#define DC_bop_SHIFT 16
|
||||
#define DC_trans_SHIFT 20
|
||||
#define DC_bltmod_bmonolef 0x0
|
||||
#define DC_bltmod_bmonowf 0x8000000
|
||||
#define DC_bltmod_bplan 0x2000000
|
||||
#define DC_bltmod_bfcol 0x4000000
|
||||
#define DC_bltmod_bu32bgr 0x6000000
|
||||
#define DC_bltmod_bu32rgb 0xe000000
|
||||
#define DC_bltmod_bu24bgr 0x16000000
|
||||
#define DC_bltmod_bu24rgb 0x1e000000
|
||||
#define DC_pattern_disable 0x0
|
||||
#define DC_pattern_enable 0x20000000
|
||||
#define DC_transc_disable 0x0
|
||||
#define DC_transc_enable 0x40000000
|
||||
#define DC_clipdis_disable 0x0
|
||||
#define DC_clipdis_enable 0x80000000
|
||||
|
||||
|
||||
#define SETADD_mode_vertlist 0x0
|
||||
|
||||
|
||||
#define MGA_CLEAR_CMD (DC_opcod_trap | DC_arzero_enable | \
|
||||
DC_sgnzero_enable | DC_shftzero_enable | \
|
||||
(0xC << DC_bop_SHIFT) | DC_clipdis_enable | \
|
||||
DC_solid_enable | DC_transc_enable)
|
||||
|
||||
|
||||
#define MGA_COPY_CMD (DC_opcod_bitblt | DC_atype_rpl | DC_linear_xy | \
|
||||
DC_solid_disable | DC_arzero_disable | \
|
||||
DC_sgnzero_enable | DC_shftzero_enable | \
|
||||
(0xC << DC_bop_SHIFT) | DC_bltmod_bfcol | \
|
||||
DC_pattern_disable | DC_transc_disable | \
|
||||
DC_clipdis_enable) \
|
||||
|
||||
#define MGA_FLUSH_CMD (DC_opcod_texture_trap | (0xF << DC_trans_SHIFT) |\
|
||||
DC_arzero_enable | DC_sgnzero_enable | \
|
||||
DC_atype_i)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -825,6 +825,8 @@ int mga_dma_clear( struct inode *inode, struct file *filp,
|
|||
if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
|
||||
|
||||
WRAP_TEST_WITH_RETURN( dev_priv );
|
||||
|
||||
mga_dma_dispatch_clear( dev, &clear );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
|
|
@ -847,6 +849,8 @@ int mga_dma_swap( struct inode *inode, struct file *filp,
|
|||
if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
|
||||
|
||||
WRAP_TEST_WITH_RETURN( dev_priv );
|
||||
|
||||
mga_dma_dispatch_swap( dev );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
|
|
@ -890,6 +894,8 @@ int mga_dma_vertex( struct inode *inode, struct file *filp,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
WRAP_TEST_WITH_RETURN( dev_priv );
|
||||
|
||||
mga_dma_dispatch_vertex( dev, buf );
|
||||
|
||||
return 0;
|
||||
|
|
@ -929,6 +935,8 @@ int mga_dma_indices( struct inode *inode, struct file *filp,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
WRAP_TEST_WITH_RETURN( dev_priv );
|
||||
|
||||
mga_dma_dispatch_indices( dev, buf, indices.start, indices.end );
|
||||
|
||||
return 0;
|
||||
|
|
@ -966,6 +974,8 @@ int mga_dma_iload( struct inode *inode, struct file *filp,
|
|||
DRM_INFO( " verifying iload... done.\n" );
|
||||
#endif
|
||||
|
||||
WRAP_TEST_WITH_RETURN( dev_priv );
|
||||
|
||||
mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue