mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-23 02:48:14 +02:00
Latest development work. Should be reasonably stable with the DRIScreenInit
locking fix. Usual caveats apply to using development code. Includes: - ctx->Texture.Enabled to ctx->Texture.ReallyEnabled fix - More useful information in GL_RENDERER string - More indirect buffer support work
This commit is contained in:
Gareth Hughes
parent
9b1f5e1d08
commit
05ef8effbf
9 changed files with 290 additions and 22 deletions
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@ -37,7 +37,7 @@
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#define R128_NAME "r128"
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#define R128_DESC "ATI Rage 128"
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#define R128_DATE "20001016"
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#define R128_DATE "20001019"
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#define R128_MAJOR 1
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#define R128_MINOR 1
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#define R128_PATCHLEVEL 0
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@ -117,6 +117,7 @@ static drm_ioctl_desc_t r128_ioctls[] = {
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[DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)] = { r128_cce_swap, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)] = { r128_cce_clear, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)] = { r128_cce_blit, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_PACKET)] = { r128_cce_packet, 1, 0 },
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};
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#define R128_IOCTL_COUNT DRM_ARRAY_SIZE(r128_ioctls)
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@ -371,6 +371,7 @@ typedef struct drm_agp_info {
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#define DRM_IOCTL_R128_SWAP DRM_IO( 0x46)
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#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x47, drm_r128_clear_t)
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#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x48, drm_r128_vertex_t)
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#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x49, drm_r128_packet_t)
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#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x49, drm_r128_blit_t)
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#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x50, drm_r128_packet_t)
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#endif
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@ -491,7 +491,8 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
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R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
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dev_priv->sarea_priv->last_dispatch = 0;
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R128_WRITE( R128_LAST_VB_REG, dev_priv->sarea_priv->last_dispatch );
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R128_WRITE( R128_LAST_DISPATCH_REG,
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dev_priv->sarea_priv->last_dispatch );
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r128_cce_init_ring_buffer( dev );
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r128_cce_load_microcode( dev_priv );
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@ -732,11 +733,12 @@ drm_buf_t *r128_freelist_get( drm_device_t *dev )
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for ( i = 0 ; i < dma->buf_count ; i++ ) {
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buf = dma->buflist[i];
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buf_priv = buf->dev_private;
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if ( buf->pid == 0 ) return buf;
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if ( buf->pid == 0 )
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return buf;
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}
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for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
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u32 done_age = R128_READ( R128_LAST_VB_REG );
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u32 done_age = R128_READ( R128_LAST_DISPATCH_REG );
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for ( i = 0 ; i < dma->buf_count ; i++ ) {
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buf = dma->buflist[i];
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@ -752,7 +754,7 @@ drm_buf_t *r128_freelist_get( drm_device_t *dev )
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udelay( 1 );
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}
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DRM_ERROR( "%s: returning NULL!\n", __FUNCTION__ );
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DRM_ERROR( "returning NULL!\n" );
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return NULL;
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}
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@ -1152,7 +1154,7 @@ static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d )
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for ( i = d->granted_count ; i < d->request_count ; i++ ) {
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buf = r128_freelist_get( dev );
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if ( !buf ) break;
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if ( !buf ) return -EAGAIN;
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buf->pid = current->pid;
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@ -58,6 +58,14 @@
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#define R128_BACK 0x2
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#define R128_DEPTH 0x4
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/* Vertex/indirect buffer size
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*/
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#define R128_BUFFER_SIZE 16384
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/* 2048x2048 @ 32bpp texture requires this many indirect buffers
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*/
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#define R128_MAX_BLIT_BUFFERS 256
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/* Keep these small for testing.
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*/
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#define R128_NR_SAREA_CLIPRECTS 12
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@ -195,11 +203,26 @@ typedef struct drm_r128_clear {
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} drm_r128_clear_t;
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typedef struct drm_r128_vertex {
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int index; /* Index of vertex buffer */
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int idx; /* Index of vertex buffer */
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int used; /* Amount of buffer used */
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int discard; /* Client finished with buffer? */
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} drm_r128_vertex_t;
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typedef struct drm_r128_blit_rect {
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int index;
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unsigned short x, y;
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unsigned short width, height;
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int padding;
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} drm_r128_blit_rect_t;
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typedef struct drm_r128_blit {
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int pitch;
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int offset;
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int format;
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drm_r128_blit_rect_t *rects;
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int count;
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} drm_r128_blit_t;
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typedef struct drm_r128_packet {
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unsigned int *buffer;
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int count;
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@ -37,7 +37,7 @@
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#define R128_NAME "r128"
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#define R128_DESC "ATI Rage 128"
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#define R128_DATE "20001016"
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#define R128_DATE "20001019"
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#define R128_MAJOR 1
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#define R128_MINOR 1
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#define R128_PATCHLEVEL 0
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@ -117,6 +117,7 @@ static drm_ioctl_desc_t r128_ioctls[] = {
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[DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)] = { r128_cce_swap, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)] = { r128_cce_clear, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)] = { r128_cce_blit, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_PACKET)] = { r128_cce_packet, 1, 0 },
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};
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#define R128_IOCTL_COUNT DRM_ARRAY_SIZE(r128_ioctls)
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@ -100,6 +100,20 @@ typedef struct drm_r128_buf_priv {
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drm_r128_freelist_t *list_entry;
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} drm_r128_buf_priv_t;
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#define R128_BLIT_PACKET_DATA_SIZE ((R128_BUFFER_SIZE / sizeof(u32)) - 8)
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typedef struct drm_r128_blit_packet {
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u32 header;
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u32 gui_master_cntl;
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u32 dst_pitch_offset;
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u32 fg_color;
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u32 bg_color;
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u16 x, y; /* HACK: endian specific */
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u16 width, height;
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u32 dwords;
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u32 data[R128_BLIT_PACKET_DATA_SIZE];
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} drm_r128_blit_packet_t;
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/* r128_drv.c */
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extern int r128_version( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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@ -143,6 +157,8 @@ extern int r128_cce_swap( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_cce_vertex( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_cce_blit( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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/* r128_bufs.c */
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extern int r128_addbufs(struct inode *inode, struct file *filp,
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@ -207,11 +223,14 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
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#define R128_CONSTANT_COLOR_C 0x1d34
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#define R128_DP_GUI_MASTER_CNTL 0x146c
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# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
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# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
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# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
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# define R128_GMC_BRUSH_NONE (15 << 4)
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# define R128_GMC_DST_16BPP (4 << 8)
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# define R128_GMC_DST_24BPP (5 << 8)
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# define R128_GMC_DST_32BPP (6 << 8)
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# define R128_GMC_DST_DATATYPE_SHIFT 8
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# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
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# define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
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# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
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@ -242,7 +261,10 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
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# define R128_FORCE_PIPE3D_CP (1 << 17)
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# define R128_FORCE_RCP (1 << 18)
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#define R128_PC_GUI_CTLSTAT 0x1748
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#define R128_PC_NGUI_CTLSTAT 0x0184
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# define R128_PC_FLUSH_GUI (3 << 0)
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# define R128_PC_RI_GUI (1 << 2)
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# define R128_PC_FLUSH_ALL 0x00ff
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# define R128_PC_BUSY (1 << 31)
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@ -289,6 +311,9 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
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#define R128_PM4_VC_FPU_SETUP 0x071c
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#define R128_PM4_IW_INDOFF 0x0738
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#define R128_PM4_IW_INDSIZE 0x073c
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#define R128_PM4_STAT 0x07b8
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# define R128_PM4_FIFOCNT_MASK 0x0fff
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# define R128_PM4_BUSY (1 << 16)
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@ -337,6 +362,15 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
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#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
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#define R128_CCE_VC_CNTL_NUM_SHIFT 16
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#define R128_DATATYPE_CI8 2
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#define R128_DATATYPE_ARGB1555 3
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#define R128_DATATYPE_RGB565 4
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#define R128_DATATYPE_RGB888 5
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#define R128_DATATYPE_ARGB8888 6
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#define R128_DATATYPE_RGB332 7
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#define R128_DATATYPE_RGB8 9
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#define R128_DATATYPE_ARGB4444 15
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/* Constants */
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#define R128_AGP_OFFSET 0x02000000
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@ -348,7 +382,7 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
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#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
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#define R128_LAST_VB_REG R128_GUI_SCRATCH_REG1
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#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
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#define R128_MAX_VB_AGE 0xffffffff
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@ -558,19 +558,18 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
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}
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if ( buf_priv->discard ) {
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buf_priv->age = dev_priv->sarea_priv->last_dispatch;
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/* Emit the vertex buffer age */
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BEGIN_RING( 2 );
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OUT_RING( CCE_PACKET0( R128_LAST_VB_REG, 0 ) );
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OUT_RING( dev_priv->sarea_priv->last_dispatch );
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OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
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OUT_RING( buf_priv->age );
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ADVANCE_RING();
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buf->pending = 1;
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/* FIXME: Check dispatched field */
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buf_priv->dispatched = 0;
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buf_priv->age = dev_priv->sarea_priv->last_dispatch;
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}
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dev_priv->sarea_priv->last_dispatch++;
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@ -586,6 +585,175 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
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}
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static void r128_cce_dispatch_indirect( drm_device_t *dev, drm_buf_t *buf )
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{
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drm_r128_private_t *dev_priv = dev->dev_private;
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drm_r128_buf_priv_t *buf_priv = buf->dev_private;
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int offset = dev_priv->buffers->offset + buf->offset - dev->agp->base;
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int size = ((buf->used / sizeof(u32)) + 1) & ~0x1;
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RING_LOCALS;
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DRM_DEBUG( "%s\n", __FUNCTION__ );
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r128_update_ring_snapshot( dev_priv );
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if ( buf->used ) {
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DRM_DEBUG( "%s: offset=0x%x size=%d used=%d\n",
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__FUNCTION__, offset, size, buf->used );
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buf_priv->dispatched = 1;
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/* Fire off the indirect buffer */
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BEGIN_RING( 3 );
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OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) );
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OUT_RING( offset );
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OUT_RING( size );
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ADVANCE_RING();
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}
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if ( buf_priv->discard ) {
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buf_priv->age = dev_priv->sarea_priv->last_dispatch;
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/* Emit the indirect buffer age */
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BEGIN_RING( 2 );
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OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
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OUT_RING( buf_priv->age );
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ADVANCE_RING();
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buf->pending = 1;
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/* FIXME: Check dispatched field */
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buf_priv->dispatched = 0;
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}
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dev_priv->sarea_priv->last_dispatch++;
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#if 0
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if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
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ret = r128_do_cce_idle( dev_priv );
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if ( ret < 0 ) return ret;
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dev_priv->submit_age = 0;
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r128_freelist_reset( dev );
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}
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#endif
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}
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static int r128_cce_dispatch_blit( drm_device_t *dev,
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int offset, int pitch, int format,
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drm_r128_blit_rect_t *rects, int count )
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{
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drm_r128_private_t *dev_priv = dev->dev_private;
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drm_device_dma_t *dma = dev->dma;
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drm_buf_t *buf;
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drm_r128_buf_priv_t *buf_priv;
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drm_r128_blit_rect_t *rect;
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drm_r128_blit_packet_t *blit;
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int dword_shift, dwords;
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int i;
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RING_LOCALS;
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DRM_DEBUG( "%s\n", __FUNCTION__ );
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switch ( format ) {
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case R128_DATATYPE_ARGB1555:
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case R128_DATATYPE_RGB565:
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case R128_DATATYPE_ARGB4444:
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dword_shift = 1;
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break;
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case R128_DATATYPE_ARGB8888:
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dword_shift = 0;
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break;
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default:
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DRM_ERROR( "invalid blit format %d\n", format );
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return -EINVAL;
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}
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/* Flush the pixel cache, and mark the contents as Read Invalid.
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* This ensures no pixel data gets mixed up with the texture
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* data from the host data blit, otherwise part of the texture
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* image may be corrupted.
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*/
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BEGIN_RING( 2 );
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OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
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OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI );
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ADVANCE_RING();
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/* Dispatch each of the indirect buffers.
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*/
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for ( i = 0 ; i < count ; i++ ) {
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rect = &rects[i];
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buf = dma->buflist[rect->index];
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buf_priv = buf->dev_private;
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if ( buf->pid != current->pid ) {
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DRM_ERROR( "process %d using buffer owned by %d\n",
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current->pid, buf->pid );
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return -EINVAL;
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}
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if ( buf->pending ) {
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DRM_ERROR( "sending pending buffer %d\n",
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rect->index );
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return -EINVAL;
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}
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buf_priv->discard = 1;
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dwords = (rect->width * rect->height) >> dword_shift;
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blit = (drm_r128_blit_packet_t *)
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((char *)dev_priv->buffers->handle + buf->offset);
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blit->header = CCE_PACKET3( R128_CNTL_HOSTDATA_BLT,
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dwords + 6 );
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blit->gui_master_cntl = ( R128_GMC_DST_PITCH_OFFSET_CNTL
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| R128_GMC_BRUSH_NONE
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| (format << 8)
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| R128_GMC_SRC_DATATYPE_COLOR
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| R128_ROP3_S
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| R128_DP_SRC_SOURCE_HOST_DATA
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| R128_GMC_CLR_CMP_CNTL_DIS
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| R128_GMC_AUX_CLIP_DIS
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| R128_GMC_WR_MSK_DIS );
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blit->dst_pitch_offset = (pitch << 21) | (offset >> 5);
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blit->fg_color = 0xffffffff;
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blit->bg_color = 0xffffffff;
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blit->x = rect->x;
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blit->y = rect->y;
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blit->width = rect->width;
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blit->height = rect->height;
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blit->dwords = dwords;
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/* FIXME: This should really go in the function call...
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*/
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if ( dwords & 1 ) {
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blit->data[dwords++] = R128_CCE_PACKET2;
|
||||
}
|
||||
buf->used = (dwords + 8) * sizeof(u32);
|
||||
|
||||
r128_cce_dispatch_indirect( dev, buf );
|
||||
}
|
||||
|
||||
/* Flush the pixel cache after the blit completes. This ensures
|
||||
* the texture data is written out to memory before rendering
|
||||
* continues.
|
||||
*/
|
||||
BEGIN_RING( 2 );
|
||||
|
||||
OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
|
||||
OUT_RING( R128_PC_FLUSH_GUI );
|
||||
|
||||
ADVANCE_RING();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* ================================================================
|
||||
*
|
||||
*/
|
||||
|
|
@ -679,15 +847,15 @@ int r128_cce_vertex( struct inode *inode, struct file *filp,
|
|||
|
||||
DRM_DEBUG( "%s: pid=%d index=%d used=%d discard=%d\n",
|
||||
__FUNCTION__, current->pid,
|
||||
vertex.index, vertex.used, vertex.discard );
|
||||
vertex.idx, vertex.used, vertex.discard );
|
||||
|
||||
if ( vertex.index < 0 || vertex.index >= dma->buf_count ) {
|
||||
if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
|
||||
DRM_ERROR( "buffer index %d (of %d max)\n",
|
||||
vertex.index, dma->buf_count - 1 );
|
||||
vertex.idx, dma->buf_count - 1 );
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
buf = dma->buflist[vertex.index];
|
||||
buf = dma->buflist[vertex.idx];
|
||||
buf_priv = buf->dev_private;
|
||||
|
||||
if ( buf->pid != current->pid ) {
|
||||
|
|
@ -696,7 +864,7 @@ int r128_cce_vertex( struct inode *inode, struct file *filp,
|
|||
return -EINVAL;
|
||||
}
|
||||
if ( buf->pending ) {
|
||||
DRM_ERROR( "sending pending buffer %d\n", vertex.index );
|
||||
DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -707,3 +875,39 @@ int r128_cce_vertex( struct inode *inode, struct file *filp,
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int r128_cce_blit( struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg )
|
||||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
drm_r128_blit_t blit;
|
||||
drm_r128_blit_rect_t rects[R128_MAX_BLIT_BUFFERS];
|
||||
|
||||
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
|
||||
dev->lock.pid != current->pid ) {
|
||||
DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ( copy_from_user( &blit, (drm_r128_blit_t *)arg,
|
||||
sizeof(blit) ) )
|
||||
return -EFAULT;
|
||||
|
||||
DRM_DEBUG( "%s: pid=%d count=%d\n",
|
||||
__FUNCTION__, current->pid, blit.count );
|
||||
|
||||
if ( blit.count < 0 || blit.count > dma->buf_count ) {
|
||||
DRM_ERROR( "sending %d buffers (of %d max)\n",
|
||||
blit.count, dma->buf_count );
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ( copy_from_user( &rects, blit.rects,
|
||||
blit.count * sizeof(drm_r128_blit_rect_t) ) )
|
||||
return -EFAULT;
|
||||
|
||||
return r128_cce_dispatch_blit( dev, blit.offset, blit.pitch,
|
||||
blit.format, rects, blit.count );
|
||||
}
|
||||
|
|
|
|||
|
|
@ -371,6 +371,7 @@ typedef struct drm_agp_info {
|
|||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x46)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x47, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x48, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x49, drm_r128_packet_t)
|
||||
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x49, drm_r128_blit_t)
|
||||
#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x50, drm_r128_packet_t)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -371,6 +371,7 @@ typedef struct drm_agp_info {
|
|||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x46)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x47, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x48, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x49, drm_r128_packet_t)
|
||||
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x49, drm_r128_blit_t)
|
||||
#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x50, drm_r128_packet_t)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue