2007-03-26 19:43:48 +10:00
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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int
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2007-07-13 15:09:31 +10:00
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nv40_mc_init(struct drm_device *dev)
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2007-03-26 19:43:48 +10:00
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{
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2007-07-13 15:09:31 +10:00
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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2007-03-26 19:43:48 +10:00
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uint32_t tmp;
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2007-04-06 03:03:59 +10:00
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/* Power up everything, resetting each individual unit will
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* be done later if needed.
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*/
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NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
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2007-03-26 19:43:48 +10:00
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switch (dev_priv->chipset) {
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case 0x44:
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case 0x46: /* G72 */
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case 0x4e:
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case 0x4c: /* C51_G7X */
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2009-03-24 16:42:36 +00:00
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tmp = NV_READ(NV10_PFB_CSTATUS);
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2007-03-26 19:43:48 +10:00
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NV_WRITE(NV40_PMC_1700, tmp);
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NV_WRITE(NV40_PMC_1704, 0);
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NV_WRITE(NV40_PMC_1708, 0);
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NV_WRITE(NV40_PMC_170C, tmp);
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break;
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default:
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break;
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}
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return 0;
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}
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void
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2007-07-13 15:09:31 +10:00
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nv40_mc_takedown(struct drm_device *dev)
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2007-03-26 19:43:48 +10:00
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{
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}
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