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7abbcce422
help with ati, and future DRM drivers.
- Add new "ati" kdrive driver. It has ancestry in the r128 driver from
andersca, but took a detour through being the WIP SiS 300 driver on the
way. It supports Radeons (tested on QD VIVO and 7500) and Rage 128.
Current limitations include that it requires depth 16 and that the
other Rage 128 PCI IDs aren't included yet.
337 lines
8.5 KiB
C
337 lines
8.5 KiB
C
/*
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* $Id$
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*
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* Copyright © 2003 Eric Anholt
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of Eric Anholt not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. Eric Anholt makes no
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* representations about the suitability of this software for any purpose. It
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* is provided "as is" without express or implied warranty.
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*
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* ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/* $Header$ */
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#include <sys/io.h>
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#ifdef HAVE_CONFIG_H
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#include <config.h>
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#endif
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#include "ati.h"
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#include "ati_reg.h"
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CARD8 ATISolidRop[16] = {
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/* GXclear */ 0x00, /* 0 */
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/* GXand */ 0xa0, /* src AND dst */
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/* GXandReverse */ 0x50, /* src AND NOT dst */
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/* GXcopy */ 0xf0, /* src */
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/* GXandInverted*/ 0x0a, /* NOT src AND dst */
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/* GXnoop */ 0xaa, /* dst */
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/* GXxor */ 0x5a, /* src XOR dst */
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/* GXor */ 0xfa, /* src OR dst */
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/* GXnor */ 0x05, /* NOT src AND NOT dst */
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/* GXequiv */ 0xa5, /* NOT src XOR dst */
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/* GXinvert */ 0x55, /* NOT dst */
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/* GXorReverse */ 0xf5, /* src OR NOT dst */
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/* GXcopyInverted*/ 0x0f, /* NOT src */
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/* GXorInverted */ 0xaf, /* NOT src OR dst */
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/* GXnand */ 0x5f, /* NOT src OR NOT dst */
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/* GXset */ 0xff, /* 1 */
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};
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CARD8 ATIBltRop[16] = {
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/* GXclear */ 0x00, /* 0 */
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/* GXand */ 0x88, /* src AND dst */
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/* GXandReverse */ 0x44, /* src AND NOT dst */
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/* GXcopy */ 0xcc, /* src */
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/* GXandInverted*/ 0x22, /* NOT src AND dst */
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/* GXnoop */ 0xaa, /* dst */
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/* GXxor */ 0x66, /* src XOR dst */
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/* GXor */ 0xee, /* src OR dst */
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/* GXnor */ 0x11, /* NOT src AND NOT dst */
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/* GXequiv */ 0x99, /* NOT src XOR dst */
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/* GXinvert */ 0x55, /* NOT dst */
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/* GXorReverse */ 0xdd, /* src OR NOT dst */
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/* GXcopyInverted*/ 0x33, /* NOT src */
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/* GXorInverted */ 0xbb, /* NOT src OR dst */
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/* GXnand */ 0x77, /* NOT src OR NOT dst */
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/* GXset */ 0xff, /* 1 */
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};
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int copydx, copydy;
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int is_radeon;
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int fifo_size;
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char *mmio;
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CARD32 bltCmd;
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static void
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ATIWaitAvail(int n)
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{
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if (fifo_size >= n) {
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fifo_size -= n;
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return;
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}
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if (is_radeon) {
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fifo_size = MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS) &
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RADEON_RBBM_FIFOCNT_MASK;
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while (fifo_size < n) {
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usleep(1);
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fifo_size = MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS) &
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RADEON_RBBM_FIFOCNT_MASK;
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}
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} else {
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fifo_size = MMIO_IN32(mmio, R128_REG_GUI_STAT) & 0xfff;
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while (fifo_size < n) {
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fifo_size = MMIO_IN32(mmio, R128_REG_GUI_STAT) & 0xfff;
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usleep(1);
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}
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}
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fifo_size -= n;
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}
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static void
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RadeonWaitIdle(void)
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{
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CARD32 temp;
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/* Wait for the engine to go idle */
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ATIWaitAvail(64);
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while ((MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS) &
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RADEON_RBBM_ACTIVE) != 0)
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usleep(1);
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/* Flush pixel cache */
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temp = MMIO_IN32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT);
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temp |= RADEON_RB2D_DC_FLUSH_ALL;
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MMIO_OUT32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT, temp);
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while ((MMIO_IN32(mmio, RADEON_REG_RB2D_DSTCACHE_CTLSTAT) &
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RADEON_RB2D_DC_BUSY) != 0)
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usleep(1);
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}
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static void
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R128WaitIdle(void)
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{
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CARD32 temp;
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int tries;
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ATIWaitAvail(64);
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tries = 1000000;
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while (tries--) {
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if ((MMIO_IN32(mmio, R128_REG_GUI_STAT) & R128_GUI_ACTIVE) == 0)
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break;
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}
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temp = MMIO_IN32(mmio, R128_REG_PC_NGUI_CTLSTAT);
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MMIO_OUT32(mmio, R128_REG_PC_NGUI_CTLSTAT, temp | 0xff);
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tries = 1000000;
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while (tries--) {
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if ((MMIO_IN32(mmio, R128_REG_PC_NGUI_CTLSTAT) & R128_PC_BUSY) !=
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R128_PC_BUSY)
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break;
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}
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}
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static void
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ATIWaitIdle(void)
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{
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if (is_radeon)
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RadeonWaitIdle();
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else
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R128WaitIdle();
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}
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static void
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ATISetup(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATICardInfo(pScreenPriv);
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ATIScreenInfo(pScreenPriv);
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mmio = atic->reg_base;
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ATIWaitAvail(5);
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if (is_radeon) {
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MMIO_OUT32(mmio, RADEON_REG_DEFAULT_OFFSET, atis->pitch << 16);
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} else {
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MMIO_OUT32(mmio, RADEON_REG_DEFAULT_OFFSET, 0);
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MMIO_OUT32(mmio, RADEON_REG_DEFAULT_PITCH,
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pScreenPriv->screen->width >> 3);
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}
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MMIO_OUT32(mmio, RADEON_REG_DEFAULT_SC_BOTTOM_RIGHT,
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(RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX));
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MMIO_OUT32(mmio, RADEON_REG_SC_TOP_LEFT, 0);
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MMIO_OUT32(mmio, RADEON_REG_SC_BOTTOM_RIGHT,
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RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
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}
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static Bool
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ATIPrepareSolid(PixmapPtr pPixmap, int alu, Pixel pm, Pixel fg)
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{
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KdScreenPriv(pPixmap->drawable.pScreen);
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ATIScreenInfo(pScreenPriv);
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ATISetup(pPixmap->drawable.pScreen);
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ATIWaitAvail(4);
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MMIO_OUT32(mmio, RADEON_REG_DP_GUI_MASTER_CNTL,
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atis->dp_gui_master_cntl | RADEON_GMC_BRUSH_SOLID_COLOR |
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RADEON_GMC_SRC_DATATYPE_COLOR | (ATISolidRop[alu] << 16));
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MMIO_OUT32(mmio, RADEON_REG_DP_BRUSH_FRGD_CLR, fg);
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MMIO_OUT32(mmio, RADEON_REG_DP_WRITE_MASK, pm);
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MMIO_OUT32(mmio, RADEON_REG_DP_CNTL, RADEON_DST_X_LEFT_TO_RIGHT |
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RADEON_DST_Y_TOP_TO_BOTTOM);
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return TRUE;
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}
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static void
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ATISolid(int x1, int y1, int x2, int y2)
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{
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ATIWaitAvail(2);
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MMIO_OUT32(mmio, RADEON_REG_DST_Y_X, (y1 << 16) | x1);
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MMIO_OUT32(mmio, RADEON_REG_DST_WIDTH_HEIGHT, ((x2 - x1) << 16) |
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(y2 - y1));
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}
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static void
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ATIDoneSolid(void)
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{
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}
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static Bool
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ATIPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, int dx, int dy, int alu, Pixel pm)
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{
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KdScreenPriv(pDst->drawable.pScreen);
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ATIScreenInfo(pScreenPriv);
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copydx = dx;
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copydy = dy;
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ATIWaitAvail(3);
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MMIO_OUT32(mmio, RADEON_REG_DP_GUI_MASTER_CNTL,
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atis->dp_gui_master_cntl | RADEON_GMC_BRUSH_SOLID_COLOR |
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RADEON_GMC_SRC_DATATYPE_COLOR | (ATIBltRop[alu] << 16) |
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RADEON_DP_SRC_SOURCE_MEMORY);
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MMIO_OUT32(mmio, RADEON_REG_DP_WRITE_MASK, pm);
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MMIO_OUT32(mmio, RADEON_REG_DP_CNTL,
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(dx >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
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(dy >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0));
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return TRUE;
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}
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static void
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ATICopy(int srcX, int srcY, int dstX, int dstY, int w, int h)
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{
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if (copydx < 0) {
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srcX += w - 1;
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dstX += w - 1;
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}
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if (copydy < 0) {
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srcY += h - 1;
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dstY += h - 1;
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}
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ATIWaitAvail(3);
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MMIO_OUT32(mmio, RADEON_REG_SRC_Y_X, (srcY << 16) | srcX);
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MMIO_OUT32(mmio, RADEON_REG_DST_Y_X, (dstY << 16) | dstX);
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MMIO_OUT32(mmio, RADEON_REG_DST_HEIGHT_WIDTH, (h << 16) | w);
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}
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static void
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ATIDoneCopy(void)
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{
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}
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KaaScreenInfoRec ATIKaa = {
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ATIPrepareSolid,
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ATISolid,
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ATIDoneSolid,
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ATIPrepareCopy,
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ATICopy,
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ATIDoneCopy,
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};
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Bool
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ATIDrawInit(ScreenPtr pScreen)
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{
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if (!kaaDrawInit(pScreen, &ATIKaa))
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return FALSE;
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return TRUE;
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}
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void
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ATIDrawEnable(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATIScreenInfo(pScreenPriv);
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ATICardInfo(pScreenPriv);
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is_radeon = atic->is_radeon;
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atis->pitch = pScreenPriv->screen->width *
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pScreenPriv->screen->fb[0].bitsPerPixel/8;
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/*ErrorF("depth=%d pitch=%d radeon=%d\n",
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pScreenPriv->screen->fb[0].depth, atis->pitch, is_radeon);*/
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switch (pScreenPriv->screen->fb[0].depth)
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{
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case 8:
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atis->datatype = 2;
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break;
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case 15:
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atis->datatype = 3;
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break;
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case 16:
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atis->datatype = 4;
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break;
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case 24:
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atis->datatype = 5;
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break;
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case 32:
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atis->datatype = 6;
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break;
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default:
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ErrorF("Bad depth %d\n", pScreenPriv->screen->fb[0].depth);
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}
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atis->dp_gui_master_cntl = (atis->datatype << 8) |
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RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_AUX_CLIP_DIS;
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KdMarkSync(pScreen);
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}
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void
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ATIDrawDisable(ScreenPtr pScreen)
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{
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}
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void
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ATIDrawFini(ScreenPtr pScreen)
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{
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}
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void
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ATIDrawSync(ScreenPtr pScreen)
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{
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KdScreenPriv(pScreen);
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ATICardInfo(pScreenPriv);
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mmio = atic->reg_base;
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ATIWaitIdle();
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}
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