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mesa/src/broadcom/compiler
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Eric Anholt 6a78416dab broadcom/vc5: Fix BASE_LEVEL handling with txl. 
The HW doesn't add the base level anywhere (the min/max lod clamping is
what does base level), so we need to add it manually in this case.

Fixes piglit tex-miplevel-selection *Lod 2D.
2017-11-22 10:56:31 -08:00
..
meson.build broadcom/vc5: Add lowering for txf_ms to a txf on a 2x2-scaled texture. 2017-10-30 13:31:27 -07:00
nir_to_vir.c broadcom/vc5: Fix BASE_LEVEL handling with txl. 2017-11-22 10:56:31 -08:00
qpu_schedule.c broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write. 2017-11-07 12:57:49 -08:00
qpu_validate.c broadcom: Add VC5 NIR compiler. 2017-10-10 11:42:04 -07:00
v3d_compiler.h broadcom/vc5: Add lowering for txf_ms to a txf on a 2x2-scaled texture. 2017-10-30 13:31:27 -07:00
v3d_nir_lower_io.c broadcom: Add VC5 NIR compiler. 2017-10-10 11:42:04 -07:00
v3d_nir_lower_txf_ms.c broadcom/vc5: Add lowering for txf_ms to a txf on a 2x2-scaled texture. 2017-10-30 13:31:27 -07:00
vir.c broadcom/vc5: Add lowering for txf_ms to a txf on a 2x2-scaled texture. 2017-10-30 13:31:27 -07:00
vir_dump.c broadcom: Add VC5 NIR compiler. 2017-10-10 11:42:04 -07:00
vir_live_variables.c broadcom: Add VC5 NIR compiler. 2017-10-10 11:42:04 -07:00
vir_lower_uniforms.c broadcom/vc5: Propagate vc4 aliasing fix to vc5. 2017-10-20 17:09:47 -07:00
vir_opt_copy_propagate.c broadcom: Add VC5 NIR compiler. 2017-10-10 11:42:04 -07:00
vir_opt_dead_code.c broadcom: Add VC5 NIR compiler. 2017-10-10 11:42:04 -07:00
vir_register_allocate.c broadcom: Add VC5 NIR compiler. 2017-10-10 11:42:04 -07:00
vir_to_qpu.c nir: Get rid of nir_shader::stage 2017-10-20 12:49:17 -07:00