mesa/src/intel
Caio Oliveira fd0a7efb5a spirv, nir: Delay calculation of shared_size when using explicit layout
Move the calculation to nir_lower_vars_to_explicit_types().  This
consolidates the check of shader_info::shared_memory_explicit_layout
in a single place instead of in all drivers.

This is motivated by SPV_KHR_untyped_pointers.  Before that extension
we had essentially two modes for shared memory variables

- No layout decorations in the SPIR-V, and both internal layout and
  driver location was _given by the driver_.

- Explicitly laid out, i.e. they are blocks, and decorated with Aliased.
  Because they all alias, we could assign them driver location directly
  to the start of the shared memory.

With the untyped pointers extension, there's a third option, to be added
by a later commit

- Explicitly laid out, i.e. they are blocks, and NOT decorated
  with Aliased.  Driver location is _given by the driver_.  Blocks
  with and without Aliased can be mixed.

The driver location of multiple blocks that don't alias depend on
alignment that is driver-specific, which we can more easily do from
the nir_lower_vars_to_explicit_types() that already has access to
a function to obtain such value.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> (hk)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v3dv)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (anv/hasvk)
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> (panvk)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (radv)
Reviewed-by: Rob Clark <robdclark@gmail.com> (tu)
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34139>
2025-04-17 19:13:17 +00:00
..
blorp intel: Program XY_FAST_COLOR_BLT::Destination Mocs for gfx12 2025-04-17 18:11:44 +00:00
ci ci/piglit: Use structured tagging for Piglit 2025-04-17 09:22:39 +00:00
common intel: Use devinfo->urb.min_entries[GS and TCS] for setting URB configs 2025-03-10 17:23:07 -07:00
compiler spirv, radv, intel: Add NIR intrinsic for cmat conversion 2025-04-16 23:13:36 +00:00
decoder intel/brw: support for dumping shader line numbers 2025-04-08 19:39:53 +00:00
dev intel: Disable has_bfloat16 for MTL 2025-04-14 18:23:43 +00:00
ds perfetto/android: align datasource names with tooling expectations 2025-04-08 18:29:10 +00:00
executor intel/executor: Update bfloat example 2025-04-14 18:23:43 +00:00
genxml intel: Program XY_FAST_COLOR_BLT::Destination Mocs for gfx12 2025-04-17 18:11:44 +00:00
isl isl: enable CPB compression 2025-03-28 04:38:09 +00:00
nullhw-layer build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
perf intel/perf: Update intel_perf to match xe_drm.h 2025-04-11 18:35:49 +00:00
shaders intel: use common CL args 2025-03-06 00:43:59 +00:00
tools intel/tools: fix 32b build for EU stall tool 2025-04-09 21:40:46 +00:00
vulkan spirv, nir: Delay calculation of shared_size when using explicit layout 2025-04-17 19:13:17 +00:00
vulkan_hasvk spirv, nir: Delay calculation of shared_size when using explicit layout 2025-04-17 19:13:17 +00:00
meson.build intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00