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Skylake total instructions in shared programs: 14399081 -> 14399010 (<.01%) instructions in affected programs: 26961 -> 26890 (-0.26%) helped: 57 HURT: 0 helped stats (abs) min: 1 max: 6 x̄: 1.25 x̃: 1 helped stats (rel) min: 0.16% max: 0.80% x̄: 0.30% x̃: 0.18% 95% mean confidence interval for instructions value: -1.50 -0.99 95% mean confidence interval for instructions %-change: -0.35% -0.25% Instructions are helped. total cycles in shared programs: 532978307 -> 532976050 (<.01%) cycles in affected programs: 468629 -> 466372 (-0.48%) helped: 33 HURT: 20 helped stats (abs) min: 3 max: 360 x̄: 116.52 x̃: 98 helped stats (rel) min: 0.06% max: 3.63% x̄: 1.66% x̃: 1.27% HURT stats (abs) min: 2 max: 172 x̄: 79.40 x̃: 43 HURT stats (rel) min: 0.04% max: 3.02% x̄: 1.48% x̃: 0.44% 95% mean confidence interval for cycles value: -81.29 -3.88 95% mean confidence interval for cycles %-change: -1.07% 0.12% Inconclusive result (%-change mean confidence interval includes 0). All Gen6+ platforms, except Ivy Bridge, had similar results. (Haswell shown) total instructions in shared programs: 12973897 -> 12973838 (<.01%) instructions in affected programs: 25970 -> 25911 (-0.23%) helped: 55 HURT: 0 helped stats (abs) min: 1 max: 2 x̄: 1.07 x̃: 1 helped stats (rel) min: 0.16% max: 0.62% x̄: 0.28% x̃: 0.18% 95% mean confidence interval for instructions value: -1.14 -1.00 95% mean confidence interval for instructions %-change: -0.32% -0.24% Instructions are helped. total cycles in shared programs: 410355841 -> 410352067 (<.01%) cycles in affected programs: 578454 -> 574680 (-0.65%) helped: 47 HURT: 5 helped stats (abs) min: 3 max: 360 x̄: 85.74 x̃: 18 helped stats (rel) min: 0.05% max: 3.68% x̄: 1.18% x̃: 0.38% HURT stats (abs) min: 2 max: 242 x̄: 51.20 x̃: 4 HURT stats (rel) min: <.01% max: 0.45% x̄: 0.15% x̃: 0.11% 95% mean confidence interval for cycles value: -104.89 -40.27 95% mean confidence interval for cycles %-change: -1.45% -0.66% Cycles are helped. Ivy Bridge total instructions in shared programs: 11679351 -> 11679301 (<.01%) instructions in affected programs: 28208 -> 28158 (-0.18%) helped: 50 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.12% max: 0.54% x̄: 0.23% x̃: 0.16% 95% mean confidence interval for instructions value: -1.00 -1.00 95% mean confidence interval for instructions %-change: -0.27% -0.19% Instructions are helped. total cycles in shared programs: 257445362 -> 257444662 (<.01%) cycles in affected programs: 419338 -> 418638 (-0.17%) helped: 40 HURT: 3 helped stats (abs) min: 1 max: 170 x̄: 65.05 x̃: 24 helped stats (rel) min: 0.02% max: 3.51% x̄: 1.26% x̃: 0.41% HURT stats (abs) min: 2 max: 1588 x̄: 634.00 x̃: 312 HURT stats (rel) min: 0.05% max: 2.97% x̄: 1.21% x̃: 0.62% 95% mean confidence interval for cycles value: -97.96 65.41 95% mean confidence interval for cycles %-change: -1.56% -0.62% Inconclusive result (value mean confidence interval includes 0). No changes on Iron Lake or GM45. v2: Move 'if (cond != BRW_CONDITIONAL_Z && cond != BRW_CONDITIONAL_NZ)' check outside the loop. Suggested by Iago. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
344 lines
12 KiB
C++
344 lines
12 KiB
C++
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_fs.h"
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#include "brw_cfg.h"
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#include "brw_eu.h"
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/** @file brw_fs_cmod_propagation.cpp
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*
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* Implements a pass that propagates the conditional modifier from a CMP x 0.0
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* instruction into the instruction that generated x. For instance, in this
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* sequence
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*
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* add(8) g70<1>F g69<8,8,1>F 4096F
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* cmp.ge.f0(8) null g70<8,8,1>F 0F
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*
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* we can do the comparison as part of the ADD instruction directly:
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*
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* add.ge.f0(8) g70<1>F g69<8,8,1>F 4096F
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*
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* If there had been a use of the flag register and another CMP using g70
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*
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* add.ge.f0(8) g70<1>F g69<8,8,1>F 4096F
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* (+f0) sel(8) g71<F> g72<8,8,1>F g73<8,8,1>F
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* cmp.ge.f0(8) null g70<8,8,1>F 0F
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*
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* we can recognize that the CMP is generating the flag value that already
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* exists and therefore remove the instruction.
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*/
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static bool
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cmod_propagate_cmp_to_add(const gen_device_info *devinfo, bblock_t *block,
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fs_inst *inst)
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{
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bool read_flag = false;
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foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
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if (scan_inst->opcode == BRW_OPCODE_ADD &&
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!scan_inst->is_partial_write() &&
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scan_inst->exec_size == inst->exec_size) {
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bool negate;
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/* A CMP is basically a subtraction. The result of the
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* subtraction must be the same as the result of the addition.
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* This means that one of the operands must be negated. So (a +
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* b) vs (a == -b) or (a + -b) vs (a == b).
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*/
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if ((inst->src[0].equals(scan_inst->src[0]) &&
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inst->src[1].negative_equals(scan_inst->src[1])) ||
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(inst->src[0].equals(scan_inst->src[1]) &&
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inst->src[1].negative_equals(scan_inst->src[0]))) {
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negate = false;
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} else if ((inst->src[0].negative_equals(scan_inst->src[0]) &&
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inst->src[1].equals(scan_inst->src[1])) ||
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(inst->src[0].negative_equals(scan_inst->src[1]) &&
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inst->src[1].equals(scan_inst->src[0]))) {
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negate = true;
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} else {
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goto not_match;
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}
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/* From the Sky Lake PRM Vol. 7 "Assigning Conditional Mods":
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*
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* * Note that the [post condition signal] bits generated at
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* the output of a compute are before the .sat.
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*
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* So we don't have to bail if scan_inst has saturate.
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*/
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/* Otherwise, try propagating the conditional. */
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const enum brw_conditional_mod cond =
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negate ? brw_swap_cmod(inst->conditional_mod)
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: inst->conditional_mod;
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if (scan_inst->can_do_cmod() &&
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((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
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scan_inst->conditional_mod == cond)) {
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scan_inst->conditional_mod = cond;
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inst->remove(block);
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return true;
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}
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break;
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}
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not_match:
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if (scan_inst->flags_written())
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break;
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read_flag = read_flag || scan_inst->flags_read(devinfo);
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}
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return false;
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}
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/**
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* Propagate conditional modifiers from NOT instructions
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*
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* Attempt to convert sequences like
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*
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* or(8) g78<8,8,1> g76<8,8,1>UD g77<8,8,1>UD
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* ...
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* not.nz.f0(8) null g78<8,8,1>UD
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*
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* into
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*
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* or.z.f0(8) g78<8,8,1> g76<8,8,1>UD g77<8,8,1>UD
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*/
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static bool
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cmod_propagate_not(const gen_device_info *devinfo, bblock_t *block,
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fs_inst *inst)
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{
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const enum brw_conditional_mod cond = brw_negate_cmod(inst->conditional_mod);
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bool read_flag = false;
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if (cond != BRW_CONDITIONAL_Z && cond != BRW_CONDITIONAL_NZ)
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return false;
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foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
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if (regions_overlap(scan_inst->dst, scan_inst->size_written,
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inst->src[0], inst->size_read(0))) {
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if (scan_inst->opcode != BRW_OPCODE_OR &&
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scan_inst->opcode != BRW_OPCODE_AND)
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break;
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if (scan_inst->is_partial_write() ||
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scan_inst->dst.offset != inst->src[0].offset ||
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scan_inst->exec_size != inst->exec_size)
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break;
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if (scan_inst->can_do_cmod() &&
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((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
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scan_inst->conditional_mod == cond)) {
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scan_inst->conditional_mod = cond;
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inst->remove(block);
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return true;
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}
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break;
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}
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if (scan_inst->flags_written())
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break;
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read_flag = read_flag || scan_inst->flags_read(devinfo);
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}
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return false;
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}
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static bool
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opt_cmod_propagation_local(const gen_device_info *devinfo, bblock_t *block)
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{
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bool progress = false;
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int ip = block->end_ip + 1;
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foreach_inst_in_block_reverse_safe(fs_inst, inst, block) {
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ip--;
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if ((inst->opcode != BRW_OPCODE_AND &&
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inst->opcode != BRW_OPCODE_CMP &&
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inst->opcode != BRW_OPCODE_MOV &&
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inst->opcode != BRW_OPCODE_NOT) ||
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inst->predicate != BRW_PREDICATE_NONE ||
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!inst->dst.is_null() ||
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(inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
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inst->src[0].file != UNIFORM))
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continue;
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/* An ABS source modifier can only be handled when processing a compare
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* with a value other than zero.
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*/
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if (inst->src[0].abs &&
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(inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero()))
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continue;
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/* Only an AND.NZ can be propagated. Many AND.Z instructions are
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* generated (for ir_unop_not in fs_visitor::emit_bool_to_cond_code).
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* Propagating those would require inverting the condition on the CMP.
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* This changes both the flag value and the register destination of the
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* CMP. That result may be used elsewhere, so we can't change its value
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* on a whim.
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*/
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if (inst->opcode == BRW_OPCODE_AND &&
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!(inst->src[1].is_one() &&
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inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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!inst->src[0].negate))
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continue;
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if (inst->opcode == BRW_OPCODE_MOV &&
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inst->conditional_mod != BRW_CONDITIONAL_NZ)
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continue;
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/* A CMP with a second source of zero can match with anything. A CMP
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* with a second source that is not zero can only match with an ADD
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* instruction.
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*/
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if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) {
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progress = cmod_propagate_cmp_to_add(devinfo, block, inst) || progress;
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continue;
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}
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if (inst->opcode == BRW_OPCODE_NOT) {
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progress = cmod_propagate_not(devinfo, block, inst) || progress;
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continue;
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}
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bool read_flag = false;
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foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
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if (regions_overlap(scan_inst->dst, scan_inst->size_written,
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inst->src[0], inst->size_read(0))) {
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if (scan_inst->is_partial_write() ||
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scan_inst->dst.offset != inst->src[0].offset ||
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scan_inst->exec_size != inst->exec_size)
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break;
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/* CMP's result is the same regardless of dest type. */
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if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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scan_inst->opcode == BRW_OPCODE_CMP &&
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(inst->dst.type == BRW_REGISTER_TYPE_D ||
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inst->dst.type == BRW_REGISTER_TYPE_UD)) {
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inst->remove(block);
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progress = true;
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break;
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}
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/* If the AND wasn't handled by the previous case, it isn't safe
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* to remove it.
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*/
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if (inst->opcode == BRW_OPCODE_AND)
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break;
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/* Comparisons operate differently for ints and floats */
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if (scan_inst->dst.type != inst->dst.type &&
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(scan_inst->dst.type == BRW_REGISTER_TYPE_F ||
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inst->dst.type == BRW_REGISTER_TYPE_F))
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break;
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/* If the instruction generating inst's source also wrote the
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* flag, and inst is doing a simple .nz comparison, then inst
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* is redundant - the appropriate value is already in the flag
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* register. Delete inst.
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*/
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if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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!inst->src[0].negate &&
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scan_inst->flags_written()) {
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inst->remove(block);
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progress = true;
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break;
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}
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/* The conditional mod of the CMP/CMPN instructions behaves
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* specially because the flag output is not calculated from the
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* result of the instruction, but the other way around, which
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* means that even if the condmod to propagate and the condmod
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* from the CMP instruction are the same they will in general give
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* different results because they are evaluated based on different
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* inputs.
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*/
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if (scan_inst->opcode == BRW_OPCODE_CMP ||
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scan_inst->opcode == BRW_OPCODE_CMPN)
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break;
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/* From the Sky Lake PRM Vol. 7 "Assigning Conditional Mods":
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*
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* * Note that the [post condition signal] bits generated at
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* the output of a compute are before the .sat.
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*/
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if (scan_inst->saturate)
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break;
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/* From the Sky Lake PRM, Vol 2a, "Multiply":
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*
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* "When multiplying integer data types, if one of the sources
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* is a DW, the resulting full precision data is stored in
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* the accumulator. However, if the destination data type is
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* either W or DW, the low bits of the result are written to
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* the destination register and the remaining high bits are
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* discarded. This results in undefined Overflow and Sign
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* flags. Therefore, conditional modifiers and saturation
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* (.sat) cannot be used in this case."
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*
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* We just disallow cmod propagation on all integer multiplies.
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*/
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if (!brw_reg_type_is_floating_point(scan_inst->dst.type) &&
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scan_inst->opcode == BRW_OPCODE_MUL)
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break;
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/* Otherwise, try propagating the conditional. */
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enum brw_conditional_mod cond =
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inst->src[0].negate ? brw_swap_cmod(inst->conditional_mod)
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: inst->conditional_mod;
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if (scan_inst->can_do_cmod() &&
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((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
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scan_inst->conditional_mod == cond)) {
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scan_inst->conditional_mod = cond;
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inst->remove(block);
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progress = true;
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}
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break;
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}
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if (scan_inst->flags_written())
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break;
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read_flag = read_flag || scan_inst->flags_read(devinfo);
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}
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}
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return progress;
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}
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bool
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fs_visitor::opt_cmod_propagation()
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{
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bool progress = false;
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foreach_block_reverse(block, cfg) {
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progress = opt_cmod_propagation_local(devinfo, block) || progress;
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}
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if (progress)
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invalidate_live_intervals();
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return progress;
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}
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