Qiang Yu f9d54b1d36 ac/llvm,radeonsi: lower idiv in nir ... aco does not implement these idiv ops. nir_lower_idiv is for idiv ops <= 32bit and ported from llvm amdgpu, so llvm do the same. nir_lower_divmod64 is for 64bit idiv ops. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>		2023-05-15 02:01:10 +00:00
..
addrlib	amd: update addrlib	2023-03-29 20:36:09 +00:00
ci	radv/ci: stop setting MESA_SPIRV_LOG_LEVEL	2023-05-10 10:32:47 +00:00
common	ac/binary: pack prefech align code to a function	2023-05-15 02:01:10 +00:00
compiler	aco: don't treat ACCESS_NON_READABLE as ACCESS_COHERENT	2023-05-12 21:45:44 +00:00
drm-shim	amd/drm-shim: Update docs for more devices.	2023-05-12 07:44:32 +00:00
llvm	ac/llvm,radeonsi: lower idiv in nir	2023-05-15 02:01:10 +00:00
registers	amd/registers: use gfx9 packet definitions for gfx940	2023-04-06 15:00:54 +00:00
vulkan	radv: Stop running constant folding during ray query lowering	2023-05-14 17:28:40 +00:00
.clang-format	amd: Add radv_foreach_stage to ForEachMacros.	2023-03-27 08:29:35 +00:00
meson.build	meson: build radeonsi with aco	2023-05-15 02:01:10 +00:00