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f7e24e559f
For triangle geometry, the hit attributes are always two floats which contain the barycentric coordinates of the hit. For procedural geometry, they're an arbitrary blob of data passed from the intersection shader to the hit shaders. In our implementation, we stash that data right after the HW RayQuery in the ray stack. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
528 lines
20 KiB
C
528 lines
20 KiB
C
/*
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* Copyright © 2020 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_nir_rt.h"
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#include "brw_nir_rt_builder.h"
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static bool
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resize_deref(nir_builder *b, nir_deref_instr *deref,
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unsigned num_components, unsigned bit_size)
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{
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assert(deref->dest.is_ssa);
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if (deref->dest.ssa.num_components == num_components &&
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deref->dest.ssa.bit_size == bit_size)
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return false;
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/* NIR requires array indices have to match the deref bit size */
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if (deref->dest.ssa.bit_size != bit_size &&
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(deref->deref_type == nir_deref_type_array ||
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deref->deref_type == nir_deref_type_ptr_as_array)) {
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b->cursor = nir_before_instr(&deref->instr);
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assert(deref->arr.index.is_ssa);
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nir_ssa_def *idx;
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if (nir_src_is_const(deref->arr.index)) {
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idx = nir_imm_intN_t(b, nir_src_as_int(deref->arr.index), bit_size);
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} else {
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idx = nir_i2i(b, deref->arr.index.ssa, bit_size);
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}
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nir_instr_rewrite_src(&deref->instr, &deref->arr.index,
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nir_src_for_ssa(idx));
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}
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deref->dest.ssa.num_components = num_components;
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deref->dest.ssa.bit_size = bit_size;
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return true;
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}
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static bool
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lower_rt_io_derefs(nir_shader *shader)
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{
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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bool progress = false;
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unsigned num_shader_call_vars = 0;
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nir_foreach_variable_with_modes(var, shader, nir_var_shader_call_data)
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num_shader_call_vars++;
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unsigned num_ray_hit_attrib_vars = 0;
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nir_foreach_variable_with_modes(var, shader, nir_var_ray_hit_attrib)
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num_ray_hit_attrib_vars++;
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/* At most one payload is allowed because it's an input. Technically, this
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* is also true for hit attribute variables. However, after we inline an
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* any-hit shader into an intersection shader, we can end up with multiple
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* hit attribute variables. They'll end up mapping to a cast from the same
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* base pointer so this is fine.
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*/
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assert(num_shader_call_vars <= 1);
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nir_builder b;
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nir_builder_init(&b, impl);
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b.cursor = nir_before_cf_list(&impl->body);
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nir_ssa_def *call_data_addr = NULL;
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if (num_shader_call_vars > 0) {
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assert(shader->scratch_size >= BRW_BTD_STACK_CALLEE_DATA_SIZE);
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call_data_addr =
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brw_nir_rt_load_scratch(&b, BRW_BTD_STACK_CALL_DATA_PTR_OFFSET, 8,
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1, 64);
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progress = true;
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}
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gl_shader_stage stage = shader->info.stage;
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nir_ssa_def *hit_attrib_addr = NULL;
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if (num_ray_hit_attrib_vars > 0) {
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assert(stage == MESA_SHADER_ANY_HIT ||
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stage == MESA_SHADER_CLOSEST_HIT ||
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stage == MESA_SHADER_INTERSECTION);
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nir_ssa_def *hit_addr =
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brw_nir_rt_mem_hit_addr(&b, stage == MESA_SHADER_CLOSEST_HIT);
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/* The vec2 barycentrics are in 2nd and 3rd dwords of MemHit */
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nir_ssa_def *bary_addr = nir_iadd_imm(&b, hit_addr, 4);
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hit_attrib_addr = nir_bcsel(&b, nir_load_leaf_procedural_intel(&b),
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brw_nir_rt_hit_attrib_data_addr(&b),
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bary_addr);
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progress = true;
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}
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_deref)
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continue;
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nir_deref_instr *deref = nir_instr_as_deref(instr);
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if (nir_deref_mode_is(deref, nir_var_shader_call_data)) {
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deref->modes = nir_var_function_temp;
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if (deref->deref_type == nir_deref_type_var) {
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b.cursor = nir_before_instr(&deref->instr);
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nir_deref_instr *cast =
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nir_build_deref_cast(&b, call_data_addr,
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nir_var_function_temp,
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deref->var->type, 0);
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nir_ssa_def_rewrite_uses(&deref->dest.ssa,
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nir_src_for_ssa(&cast->dest.ssa));
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nir_instr_remove(&deref->instr);
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progress = true;
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}
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} else if (nir_deref_mode_is(deref, nir_var_ray_hit_attrib)) {
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deref->modes = nir_var_function_temp;
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if (deref->deref_type == nir_deref_type_var) {
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b.cursor = nir_before_instr(&deref->instr);
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nir_deref_instr *cast =
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nir_build_deref_cast(&b, hit_attrib_addr,
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nir_var_function_temp,
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deref->type, 0);
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nir_ssa_def_rewrite_uses(&deref->dest.ssa,
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nir_src_for_ssa(&cast->dest.ssa));
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nir_instr_remove(&deref->instr);
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progress = true;
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}
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}
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/* We're going to lower all function_temp memory to scratch using
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* 64-bit addresses. We need to resize all our derefs first or else
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* nir_lower_explicit_io will have a fit.
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*/
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if (nir_deref_mode_is(deref, nir_var_function_temp) &&
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resize_deref(&b, deref, 1, 64))
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progress = true;
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}
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}
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if (progress) {
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nir_metadata_preserve(impl, nir_metadata_block_index |
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nir_metadata_dominance);
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} else {
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nir_metadata_preserve(impl, nir_metadata_all);
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}
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return progress;
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}
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/** Lowers ray-tracing shader I/O and scratch access
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*
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* SPV_KHR_ray_tracing adds three new types of I/O, each of which need their
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* own bit of special care:
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*
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* - Shader payload data: This is represented by the IncomingCallableData
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* and IncomingRayPayload storage classes which are both represented by
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* nir_var_call_data in NIR. There is at most one of these per-shader and
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* they contain payload data passed down the stack from the parent shader
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* when it calls executeCallable() or traceRay(). In our implementation,
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* the actual storage lives in the calling shader's scratch space and we're
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* passed a pointer to it.
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*
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* - Hit attribute data: This is represented by the HitAttribute storage
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* class in SPIR-V and nir_var_ray_hit_attrib in NIR. For triangle
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* geometry, it's supposed to contain two floats which are the barycentric
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* coordinates. For AABS/procedural geometry, it contains the hit data
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* written out by the intersection shader. In our implementation, it's a
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* 64-bit pointer which points either to the u/v area of the relevant
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* MemHit data structure or the space right after the HW ray stack entry.
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*
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* - Shader record buffer data: This allows read-only access to the data
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* stored in the SBT right after the bindless shader handles. It's
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* effectively a UBO with a magic address. Coming out of spirv_to_nir,
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* we get a nir_intrinsic_load_shader_record_ptr which is cast to a
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* nir_var_mem_global deref and all access happens through that. The
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* shader_record_ptr system value is handled in brw_nir_lower_rt_intrinsics
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* and we assume nir_lower_explicit_io is called elsewhere thanks to
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* VK_KHR_buffer_device_address so there's really nothing to do here.
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*
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* We also handle lowering any remaining function_temp variables to scratch at
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* this point. This gets rid of any remaining arrays and also takes care of
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* the sending side of ray payloads where we pass pointers to a function_temp
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* variable down the call stack.
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*/
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static void
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lower_rt_io_and_scratch(nir_shader *nir)
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{
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/* First, we to ensure all the I/O variables have explicit types. Because
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* these are shader-internal and don't come in from outside, they don't
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* have an explicit memory layout and we have to assign them one.
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*/
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NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
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nir_var_function_temp |
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nir_var_shader_call_data |
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nir_var_ray_hit_attrib,
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glsl_get_natural_size_align_bytes);
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/* Now patch any derefs to I/O vars */
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NIR_PASS_V(nir, lower_rt_io_derefs);
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/* Finally, lower any remaining function_temp, mem_constant, or
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* ray_hit_attrib access to 64-bit global memory access.
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*/
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NIR_PASS_V(nir, nir_lower_explicit_io,
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nir_var_function_temp |
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nir_var_mem_constant |
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nir_var_ray_hit_attrib,
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nir_address_format_64bit_global);
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}
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static void
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build_terminate_ray(nir_builder *b)
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{
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nir_ssa_def *skip_closest_hit =
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nir_i2b(b, nir_iand_imm(b, nir_load_ray_flags(b),
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BRW_RT_RAY_FLAG_SKIP_CLOSEST_HIT_SHADER));
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nir_push_if(b, skip_closest_hit);
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{
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/* The shader that calls traceRay() is unable to access any ray hit
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* information except for that which is explicitly written into the ray
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* payload by shaders invoked during the trace. If there's no closest-
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* hit shader, then accepting the hit has no observable effect; it's
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* just extra memory traffic for no reason.
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*/
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brw_nir_btd_return(b);
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nir_jump(b, nir_jump_halt);
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}
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nir_push_else(b, NULL);
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{
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/* The closest hit shader is in the same shader group as the any-hit
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* shader that we're currently in. We can get the address for its SBT
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* handle by looking at the shader record pointer and subtracting the
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* size of a SBT handle. The BINDLESS_SHADER_RECORD for a closest hit
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* shader is the first one in the SBT handle.
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*/
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nir_ssa_def *closest_hit =
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nir_iadd_imm(b, nir_load_shader_record_ptr(b),
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-BRW_RT_SBT_HANDLE_SIZE);
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brw_nir_rt_commit_hit(b);
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brw_nir_btd_spawn(b, closest_hit);
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nir_jump(b, nir_jump_halt);
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}
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nir_pop_if(b, NULL);
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}
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/** Lowers away ray walk intrinsics
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*
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* This lowers terminate_ray, ignore_ray_intersection, and the NIR-specific
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* accept_ray_intersection intrinsics to the appropriate Intel-specific
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* intrinsics.
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*/
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static bool
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lower_ray_walk_intrinsics(nir_shader *shader,
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const struct gen_device_info *devinfo)
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{
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assert(shader->info.stage == MESA_SHADER_ANY_HIT ||
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shader->info.stage == MESA_SHADER_INTERSECTION);
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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nir_builder b;
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nir_builder_init(&b, impl);
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bool progress = false;
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nir_foreach_block_safe(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_ignore_ray_intersection: {
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b.cursor = nir_instr_remove(&intrin->instr);
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/* We put the newly emitted code inside a dummy if because it's
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* going to contain a jump instruction and we don't want to deal
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* with that mess here. It'll get dealt with by our control-flow
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* optimization passes.
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*/
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nir_push_if(&b, nir_imm_true(&b));
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nir_intrinsic_instr *ray_continue =
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nir_intrinsic_instr_create(b.shader,
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nir_intrinsic_trace_ray_continue_intel);
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nir_builder_instr_insert(&b, &ray_continue->instr);
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nir_jump(&b, nir_jump_halt);
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nir_pop_if(&b, NULL);
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progress = true;
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break;
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}
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case nir_intrinsic_accept_ray_intersection: {
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b.cursor = nir_instr_remove(&intrin->instr);
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nir_ssa_def *terminate =
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nir_i2b(&b, nir_iand_imm(&b, nir_load_ray_flags(&b),
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BRW_RT_RAY_FLAG_TERMINATE_ON_FIRST_HIT));
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nir_push_if(&b, terminate);
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{
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build_terminate_ray(&b);
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}
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nir_push_else(&b, NULL);
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{
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nir_intrinsic_instr *ray_commit =
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nir_intrinsic_instr_create(b.shader,
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nir_intrinsic_trace_ray_commit_intel);
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nir_builder_instr_insert(&b, &ray_commit->instr);
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nir_jump(&b, nir_jump_halt);
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}
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nir_pop_if(&b, NULL);
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progress = true;
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break;
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}
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case nir_intrinsic_terminate_ray: {
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b.cursor = nir_instr_remove(&intrin->instr);
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build_terminate_ray(&b);
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progress = true;
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break;
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}
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default:
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break;
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}
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}
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}
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if (progress) {
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nir_metadata_preserve(impl, nir_metadata_none);
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} else {
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nir_metadata_preserve(impl, nir_metadata_all);
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}
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return progress;
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}
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void
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brw_nir_lower_raygen(nir_shader *nir)
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{
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assert(nir->info.stage == MESA_SHADER_RAYGEN);
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NIR_PASS_V(nir, brw_nir_lower_shader_returns);
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lower_rt_io_and_scratch(nir);
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}
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void
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brw_nir_lower_any_hit(nir_shader *nir, const struct gen_device_info *devinfo)
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{
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assert(nir->info.stage == MESA_SHADER_ANY_HIT);
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NIR_PASS_V(nir, brw_nir_lower_shader_returns);
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NIR_PASS_V(nir, lower_ray_walk_intrinsics, devinfo);
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lower_rt_io_and_scratch(nir);
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}
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void
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brw_nir_lower_closest_hit(nir_shader *nir)
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{
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assert(nir->info.stage == MESA_SHADER_CLOSEST_HIT);
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NIR_PASS_V(nir, brw_nir_lower_shader_returns);
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lower_rt_io_and_scratch(nir);
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}
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void
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brw_nir_lower_miss(nir_shader *nir)
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{
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assert(nir->info.stage == MESA_SHADER_MISS);
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NIR_PASS_V(nir, brw_nir_lower_shader_returns);
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lower_rt_io_and_scratch(nir);
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}
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void
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brw_nir_lower_callable(nir_shader *nir)
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{
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assert(nir->info.stage == MESA_SHADER_CALLABLE);
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NIR_PASS_V(nir, brw_nir_lower_shader_returns);
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lower_rt_io_and_scratch(nir);
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}
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void
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brw_nir_lower_combined_intersection_any_hit(nir_shader *intersection,
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const nir_shader *any_hit,
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const struct gen_device_info *devinfo)
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{
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assert(intersection->info.stage == MESA_SHADER_INTERSECTION);
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assert(any_hit == NULL || any_hit->info.stage == MESA_SHADER_ANY_HIT);
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NIR_PASS_V(intersection, brw_nir_lower_shader_returns);
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NIR_PASS_V(intersection, brw_nir_lower_intersection_shader,
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any_hit, devinfo);
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NIR_PASS_V(intersection, lower_ray_walk_intrinsics, devinfo);
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lower_rt_io_and_scratch(intersection);
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}
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static nir_ssa_def *
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build_load_uniform(nir_builder *b, unsigned offset,
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unsigned num_components, unsigned bit_size)
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{
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nir_intrinsic_instr *load =
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nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
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load->num_components = num_components;
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load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
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nir_intrinsic_set_base(load, offset);
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nir_intrinsic_set_range(load, num_components * bit_size / 8);
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nir_ssa_dest_init(&load->instr, &load->dest,
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num_components, bit_size, NULL);
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nir_builder_instr_insert(b, &load->instr);
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return &load->dest.ssa;
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}
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#define load_trampoline_param(b, name, num_components, bit_size) \
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build_load_uniform((b), offsetof(struct brw_rt_raygen_trampoline_params, name), \
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(num_components), (bit_size))
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nir_shader *
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brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler,
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void *mem_ctx)
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{
|
|
const struct gen_device_info *devinfo = compiler->devinfo;
|
|
const nir_shader_compiler_options *nir_options =
|
|
compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions;
|
|
|
|
STATIC_ASSERT(sizeof(struct brw_rt_raygen_trampoline_params) == 32);
|
|
|
|
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE,
|
|
nir_options,
|
|
"RT Ray-Gen Trampoline");
|
|
ralloc_steal(mem_ctx, b.shader);
|
|
|
|
b.shader->info.cs.local_size_variable = true;
|
|
|
|
/* The RT global data and raygen BINDLESS_SHADER_RECORD addresses are
|
|
* passed in as push constants in the first register. We deal with the
|
|
* raygen BSR address here; the global data we'll deal with later.
|
|
*/
|
|
b.shader->num_uniforms = 32;
|
|
nir_ssa_def *raygen_bsr_addr =
|
|
load_trampoline_param(&b, raygen_bsr_addr, 1, 64);
|
|
nir_ssa_def *local_shift =
|
|
nir_u2u32(&b, load_trampoline_param(&b, local_group_size_log2, 3, 8));
|
|
|
|
nir_ssa_def *global_id = nir_load_work_group_id(&b, 32);
|
|
nir_ssa_def *simd_channel = nir_load_subgroup_invocation(&b);
|
|
nir_ssa_def *local_x =
|
|
nir_ubfe(&b, simd_channel, nir_imm_int(&b, 0),
|
|
nir_channel(&b, local_shift, 0));
|
|
nir_ssa_def *local_y =
|
|
nir_ubfe(&b, simd_channel, nir_channel(&b, local_shift, 0),
|
|
nir_channel(&b, local_shift, 1));
|
|
nir_ssa_def *local_z =
|
|
nir_ubfe(&b, simd_channel,
|
|
nir_iadd(&b, nir_channel(&b, local_shift, 0),
|
|
nir_channel(&b, local_shift, 1)),
|
|
nir_channel(&b, local_shift, 2));
|
|
nir_ssa_def *launch_id =
|
|
nir_iadd(&b, nir_ishl(&b, global_id, local_shift),
|
|
nir_vec3(&b, local_x, local_y, local_z));
|
|
|
|
nir_ssa_def *launch_size = nir_load_ray_launch_size(&b);
|
|
nir_push_if(&b, nir_ball(&b, nir_ult(&b, launch_id, launch_size)));
|
|
{
|
|
nir_store_global(&b, brw_nir_rt_sw_hotzone_addr(&b, devinfo), 16,
|
|
nir_vec4(&b, nir_imm_int(&b, 0), /* Stack ptr */
|
|
nir_channel(&b, launch_id, 0),
|
|
nir_channel(&b, launch_id, 1),
|
|
nir_channel(&b, launch_id, 2)),
|
|
0xf /* write mask */);
|
|
|
|
brw_nir_btd_spawn(&b, raygen_bsr_addr);
|
|
}
|
|
nir_push_else(&b, NULL);
|
|
{
|
|
/* Even though these invocations aren't being used for anything, the
|
|
* hardware allocated stack IDs for them. They need to retire them.
|
|
*/
|
|
brw_nir_btd_retire(&b);
|
|
}
|
|
nir_pop_if(&b, NULL);
|
|
|
|
nir_shader *nir = b.shader;
|
|
nir->info.name = ralloc_strdup(nir, "RT: TraceRay trampoline");
|
|
nir_validate_shader(nir, "in brw_nir_create_raygen_trampoline");
|
|
brw_preprocess_nir(compiler, nir, NULL);
|
|
|
|
NIR_PASS_V(nir, brw_nir_lower_rt_intrinsics, devinfo);
|
|
|
|
/* brw_nir_lower_rt_intrinsics will leave us with a btd_global_arg_addr
|
|
* intrinsic which doesn't exist in compute shaders. We also created one
|
|
* above when we generated the BTD spawn intrinsic. Now we go through and
|
|
* replace them with a uniform load.
|
|
*/
|
|
nir_foreach_block(block, b.impl) {
|
|
nir_foreach_instr_safe(instr, block) {
|
|
if (instr->type != nir_instr_type_intrinsic)
|
|
continue;
|
|
|
|
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
|
|
if (intrin->intrinsic != nir_intrinsic_load_btd_global_arg_addr_intel)
|
|
continue;
|
|
|
|
b.cursor = nir_before_instr(&intrin->instr);
|
|
nir_ssa_def *global_arg_addr =
|
|
load_trampoline_param(&b, rt_disp_globals_addr, 1, 64);
|
|
assert(intrin->dest.is_ssa);
|
|
nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
|
|
nir_src_for_ssa(global_arg_addr));
|
|
nir_instr_remove(instr);
|
|
}
|
|
}
|
|
|
|
NIR_PASS_V(nir, brw_nir_lower_cs_intrinsics);
|
|
|
|
brw_nir_optimize(nir, compiler, true, false);
|
|
|
|
return nir;
|
|
}
|