mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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3c5ec268ec
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38187>
294 lines
14 KiB
C
294 lines
14 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef AC_CMDBUF_H
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#define AC_CMDBUF_H
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#include <inttypes.h>
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#include "ac_pm4.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct ac_cmdbuf {
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uint32_t cdw; /* Number of used dwords. */
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uint32_t max_dw; /* Maximum number of dwords. */
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uint32_t reserved_dw; /* Number of dwords reserved. */
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uint32_t *buf; /* The base pointer of the chunk. */
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};
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/* The structure layout is identical to a pair of registers in SET_*_REG_PAIRS_PACKED. */
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struct ac_gfx11_reg_pair {
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union {
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/* A pair of register offsets. */
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struct {
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uint16_t reg_offset[2];
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};
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/* The same pair of register offsets as a dword. */
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uint32_t reg_offsets;
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};
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/* A pair of register values for the register offsets above. */
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uint32_t reg_value[2];
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};
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/* A pair of values for SET_*_REG_PAIRS. */
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struct ac_gfx12_reg {
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uint32_t reg_offset;
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uint32_t reg_value;
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};
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/* GFX11+: Buffered SH registers for SET_SH_REG_PAIRS_*. */
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struct ac_buffered_sh_regs {
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uint32_t num;
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union {
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struct {
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struct ac_gfx11_reg_pair regs[32];
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} gfx11;
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struct {
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struct ac_gfx12_reg regs[256];
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} gfx12;
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};
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};
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#define ac_cmdbuf_begin(cs) struct ac_cmdbuf *__cs = (cs); \
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uint32_t __cs_num = __cs->cdw; \
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UNUSED uint32_t __cs_num_initial = __cs_num; \
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UNUSED uint32_t __cs_reserved_dw = __cs->reserved_dw; \
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UNUSED uint32_t *__cs_buf = __cs->buf
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#define ac_cmdbuf_begin_again(cs) do { \
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assert(__cs == NULL); \
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__cs = (cs); \
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__cs_num = __cs->cdw; \
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__cs_num_initial = __cs_num; \
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__cs_buf = __cs->buf; \
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} while (0)
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#define ac_cmdbuf_emit(value) \
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do { \
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assert(!__cs_reserved_dw || __cs_num < __cs_reserved_dw); \
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__cs_buf[__cs_num++] = (value); \
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} while (0)
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#define ac_cmdbuf_packets_added() (__cs_num != __cs_num_initial)
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#define ac_cmdbuf_emit_array(values, num) do { \
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unsigned __n = (num); \
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assert(!__cs_reserved_dw || __cs_num + __n <= __cs_reserved_dw); \
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memcpy(__cs_buf + __cs_num, (values), __n * 4); \
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__cs_num += __n; \
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} while (0)
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#define ac_cmdbuf_end() do { \
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__cs->cdw = __cs_num; \
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assert(__cs->cdw <= __cs->max_dw); \
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__cs = NULL; \
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} while (0)
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/* Packet building helpers. Don't use directly. */
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#define __ac_cmdbuf_set_reg_seq(reg, num, idx, prefix_name, packet, reset_filter_cam) \
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do { \
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assert((reg) >= prefix_name##_REG_OFFSET && (reg) < prefix_name##_REG_END); \
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ac_cmdbuf_emit(PKT3(packet, num, 0) | PKT3_RESET_FILTER_CAM_S(reset_filter_cam)); \
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ac_cmdbuf_emit((((reg) - prefix_name##_REG_OFFSET) >> 2) | ((idx) << 28)); \
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} while (0)
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#define __ac_cmdbuf_set_reg(reg, idx, value, prefix_name, packet) \
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do { \
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__ac_cmdbuf_set_reg_seq(reg, 1, idx, prefix_name, packet, 0); \
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ac_cmdbuf_emit(value); \
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} while (0)
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/* Packet building helpers for CONFIG registers. */
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#define ac_cmdbuf_set_config_reg_seq(reg, num) __ac_cmdbuf_set_reg_seq(reg, num, 0, SI_CONFIG, PKT3_SET_CONFIG_REG, 0)
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#define ac_cmdbuf_set_config_reg(reg, value) __ac_cmdbuf_set_reg(reg, 0, value, SI_CONFIG, PKT3_SET_CONFIG_REG)
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/* Packet building helpers for UCONFIG registers. */
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#define ac_cmdbuf_set_uconfig_reg_seq(reg, num) __ac_cmdbuf_set_reg_seq(reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, 0)
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#define ac_cmdbuf_set_uconfig_reg(reg, value) __ac_cmdbuf_set_reg(reg, 0, value, CIK_UCONFIG, PKT3_SET_UCONFIG_REG)
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/*
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* On GFX10, there is a bug with the ME implementation of its content
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* addressable memory (CAM), that means that it can skip register writes due
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* to not taking correctly into account the fields from the GRBM_GFX_INDEX.
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* With this __filter_cam_workaround bit we can force the write.
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*/
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#define ac_cmdbuf_set_uconfig_perfctr_reg_seq(gfx_level, ip_type, reg, num) \
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do { \
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const bool __filter_cam_workaround = (gfx_level) >= GFX10 && (ip_type) == AMD_IP_GFX; \
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__ac_cmdbuf_set_reg_seq(reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, __filter_cam_workaround); \
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} while (0)
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#define ac_cmdbuf_set_uconfig_perfctr_reg(gfx_level, ip_type, reg, value) \
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do { \
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ac_cmdbuf_set_uconfig_perfctr_reg_seq(gfx_level, ip_type, reg, 1); \
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ac_cmdbuf_emit(value); \
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} while (0)
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/* Packet building helpers for CONTEXT registers. */
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#define ac_cmdbuf_set_context_reg_seq(reg, num) __ac_cmdbuf_set_reg_seq(reg, num, 0, SI_CONTEXT, PKT3_SET_CONTEXT_REG, 0)
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#define ac_cmdbuf_set_context_reg(reg, value) __ac_cmdbuf_set_reg(reg, 0, value, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
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#define ac_cmdbuf_set_context_reg_idx(reg, idx, value) __ac_cmdbuf_set_reg(reg, idx, value, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
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/* Packet building helpers for SH registers. */
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#define ac_cmdbuf_set_sh_reg_seq(reg, num) __ac_cmdbuf_set_reg_seq(reg, num, 0, SI_SH, PKT3_SET_SH_REG, 0)
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#define ac_cmdbuf_set_sh_reg(reg, value) __ac_cmdbuf_set_reg(reg, 0, value, SI_SH, PKT3_SET_SH_REG)
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#define ac_cmdbuf_event_write_predicate(event_type, predicate) \
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do { \
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unsigned __event_type = (event_type); \
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ac_cmdbuf_emit(PKT3(PKT3_EVENT_WRITE, 0, predicate)); \
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ac_cmdbuf_emit(EVENT_TYPE(__event_type) | \
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EVENT_INDEX(__event_type == V_028A90_VS_PARTIAL_FLUSH || \
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__event_type == V_028A90_PS_PARTIAL_FLUSH || \
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__event_type == V_028A90_CS_PARTIAL_FLUSH ? 4 : \
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__event_type == V_028A90_PIXEL_PIPE_STAT_CONTROL ? 1 : 0)); \
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} while (0)
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#define ac_cmdbuf_event_write(event_type) ac_cmdbuf_event_write_predicate(event_type, false)
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#define ac_cmdbuf_set_privileged_config_reg(reg, value) \
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do { \
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assert((reg) < CIK_UCONFIG_REG_OFFSET); \
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ac_cmdbuf_emit(PKT3(PKT3_COPY_DATA, 4, 0)); \
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ac_cmdbuf_emit(COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_PERF)); \
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ac_cmdbuf_emit(value); \
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ac_cmdbuf_emit(0); /* unused */ \
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ac_cmdbuf_emit((reg) >> 2); \
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ac_cmdbuf_emit(0); /* unused */ \
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} while (0)
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/* GFX11 generic packet building helpers for buffered SH registers. Don't use these directly. */
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#define ac_gfx11_push_reg(reg, value, prefix_name, buffer, reg_count) \
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do { \
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unsigned __i = (reg_count)++; \
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assert((reg) >= prefix_name##_REG_OFFSET && (reg) < prefix_name##_REG_END); \
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assert(__i / 2 < ARRAY_SIZE(buffer)); \
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buffer[__i / 2].reg_offset[__i % 2] = ((reg) - prefix_name##_REG_OFFSET) >> 2; \
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buffer[__i / 2].reg_value[__i % 2] = value; \
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} while (0)
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/* GFX11 packet building helpers for SET_CONTEXT_REG_PAIRS_PACKED.
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* Registers are buffered on the stack and then copied to the command buffer at the end.
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*/
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#define ac_gfx11_begin_packed_context_regs() \
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struct ac_gfx11_reg_pair __cs_context_regs[50]; \
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unsigned __cs_context_reg_count = 0;
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#define ac_gfx11_set_context_reg(reg, value) \
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ac_gfx11_push_reg(reg, value, SI_CONTEXT, __cs_context_regs, __cs_context_reg_count)
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#define ac_gfx11_end_packed_context_regs() \
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do { \
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if (__cs_context_reg_count >= 2) { \
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/* Align the count to 2 by duplicating the first register. */ \
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if (__cs_context_reg_count % 2 == 1) { \
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ac_gfx11_set_context_reg(SI_CONTEXT_REG_OFFSET + __cs_context_regs[0].reg_offset[0] * 4, \
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__cs_context_regs[0].reg_value[0]); \
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} \
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assert(__cs_context_reg_count % 2 == 0); \
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unsigned __num_dw = (__cs_context_reg_count / 2) * 3; \
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ac_cmdbuf_emit(PKT3(PKT3_SET_CONTEXT_REG_PAIRS_PACKED, __num_dw, 0) | PKT3_RESET_FILTER_CAM_S(1)); \
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ac_cmdbuf_emit(__cs_context_reg_count); \
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ac_cmdbuf_emit_array(__cs_context_regs, __num_dw); \
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} else if (__cs_context_reg_count == 1) { \
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ac_cmdbuf_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
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ac_cmdbuf_emit(__cs_context_regs[0].reg_offset[0]); \
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ac_cmdbuf_emit(__cs_context_regs[0].reg_value[0]); \
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} \
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} while (0)
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/* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */
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/* Reserved 1 DWORD to emit the packet header when the sequence ends. */
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#define __ac_gfx12_begin_regs(header) uint32_t header = __cs_num++
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/* Set a register unconditionally. */
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#define ac_gfx12_set_reg(reg, value, base_offset) \
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do { \
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ac_cmdbuf_emit(((reg) - (base_offset)) >> 2); \
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ac_cmdbuf_emit(value); \
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} while (0)
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/* End the sequence and emit the packet header. */
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#define __ac_gfx12_end_regs(header, packet) \
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do { \
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if ((header) + 1 == __cs_num) { \
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__cs_num--; /* no registers have been set, back off */ \
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} else { \
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unsigned __dw_count = __cs_num - (header) - 2; \
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__cs_buf[(header)] = PKT3((packet), __dw_count, 0) | PKT3_RESET_FILTER_CAM_S(1); \
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} \
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} while (0)
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/* GFX12 packet building helpers for PAIRS packets. */
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#define ac_gfx12_begin_context_regs() __ac_gfx12_begin_regs(__cs_context_reg_header)
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#define ac_gfx12_set_context_reg(reg, value) ac_gfx12_set_reg(reg, value, SI_CONTEXT_REG_OFFSET)
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#define ac_gfx12_end_context_regs() __ac_gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS)
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/* GFX12 generic packet building helpers for buffered registers. */
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#define __ac_gfx12_push_reg(buf_regs, reg, value, base_offset) \
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do { \
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unsigned __i = buf_regs.num++; \
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assert(__i < ARRAY_SIZE(buf_regs.gfx12.regs)); \
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buf_regs.gfx12.regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \
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buf_regs.gfx12.regs[__i].reg_value = value; \
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} while (0)
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#define ac_gfx12_push_sh_reg(buf_regs, reg, value) \
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__ac_gfx12_push_reg(buf_regs, reg, value, SI_SH_REG_OFFSET)
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#define ac_gfx12_push_32bit_pointer(buf_regs, sh_offset, va, info) \
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do { \
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assert((va) == 0 || ((va) >> 32) == (info)->address32_hi); \
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ac_gfx12_push_sh_reg(buf_regs, sh_offset, va); \
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} while (0)
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#define ac_gfx12_push_64bit_pointer(buf_regs, sh_offset, va) \
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do { \
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ac_gfx12_push_sh_reg(buf_regs, sh_offset, va); \
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ac_gfx12_push_sh_reg(buf_regs, sh_offset + 4, va >> 32); \
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} while (0)
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struct ac_preamble_state {
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uint64_t border_color_va;
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struct {
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bool cache_cb_gl2;
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bool cache_db_gl2;
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} gfx10;
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struct {
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uint32_t compute_dispatch_interleave;
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} gfx11;
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};
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void
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ac_init_compute_preamble_state(const struct ac_preamble_state *state,
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struct ac_pm4_state *pm4);
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void
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ac_init_graphics_preamble_state(const struct ac_preamble_state *state,
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struct ac_pm4_state *pm4);
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void
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ac_cmdbuf_flush_vgt_streamout(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level);
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#ifdef __cplusplus
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}
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#endif
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#endif
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