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https://gitlab.freedesktop.org/mesa/mesa.git
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8a39231e4f
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30169>
136 lines
2.9 KiB
C++
136 lines
2.9 KiB
C++
/*
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* Copyright 2024 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include <gtest/gtest.h>
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#include "brw_fs.h"
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#include "brw_fs_builder.h"
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#include "brw_cfg.h"
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using namespace brw;
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class cse_test : public ::testing::Test {
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protected:
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cse_test();
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~cse_test() override;
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struct brw_compiler *compiler;
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struct brw_compile_params params;
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struct intel_device_info *devinfo;
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void *ctx;
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struct brw_wm_prog_data *prog_data;
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struct gl_shader_program *shader_prog;
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fs_visitor *v;
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fs_builder bld;
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};
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class cse_fs_visitor : public fs_visitor
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{
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public:
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cse_fs_visitor(struct brw_compiler *compiler,
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struct brw_compile_params *params,
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struct brw_wm_prog_data *prog_data,
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nir_shader *shader)
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: fs_visitor(compiler, params, NULL,
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&prog_data->base, shader, 16, false, false) {}
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};
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cse_test::cse_test()
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: bld(NULL, 0)
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{
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ctx = ralloc_context(NULL);
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compiler = rzalloc(ctx, struct brw_compiler);
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devinfo = rzalloc(ctx, struct intel_device_info);
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compiler->devinfo = devinfo;
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params = {};
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params.mem_ctx = ctx;
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prog_data = ralloc(ctx, struct brw_wm_prog_data);
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nir_shader *shader =
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nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL);
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v = new cse_fs_visitor(compiler, ¶ms, prog_data, shader);
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bld = fs_builder(v).at_end();
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devinfo->verx10 = 125;
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devinfo->ver = devinfo->verx10 / 10;
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}
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cse_test::~cse_test()
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{
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delete v;
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v = NULL;
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ralloc_free(ctx);
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ctx = NULL;
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}
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static fs_inst *
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instruction(bblock_t *block, int num)
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{
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fs_inst *inst = (fs_inst *)block->start();
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for (int i = 0; i < num; i++) {
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inst = (fs_inst *)inst->next;
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}
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return inst;
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}
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static bool
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cse(fs_visitor *v)
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{
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const bool print = false;
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if (print) {
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fprintf(stderr, "= Before =\n");
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v->cfg->dump();
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}
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bool ret = brw_fs_opt_cse_defs(*v);
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if (print) {
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fprintf(stderr, "\n= After =\n");
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v->cfg->dump();
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}
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return ret;
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}
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TEST_F(cse_test, add3_invalid)
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{
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brw_reg dst0 = bld.null_reg_d();
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brw_reg src0 = bld.vgrf(BRW_TYPE_D);
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brw_reg src1 = bld.vgrf(BRW_TYPE_D);
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brw_reg src2 = bld.vgrf(BRW_TYPE_D);
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brw_reg src3 = bld.vgrf(BRW_TYPE_D);
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bld.ADD3(dst0, src0, src1, src2)
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->conditional_mod = BRW_CONDITIONAL_NZ;
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bld.ADD3(dst0, src0, src1, src3)
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->conditional_mod = BRW_CONDITIONAL_NZ;
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/* = Before =
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*
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* 0: add3.nz(16) null src0 src1 src2
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* 1: add3.nz(16) null src0 src1 src3
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*
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* = After =
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* Same
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*/
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brw_calculate_cfg(*v);
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_FALSE(cse(v));
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD3, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_OPCODE_ADD3, instruction(block0, 1)->opcode);
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}
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