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0be124b77e
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25498>
148 lines
4.1 KiB
C
148 lines
4.1 KiB
C
/*
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* Copyright 2021 Alyssa Rosenzweig
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* SPDX-License-Identifier: MIT
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*/
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#ifndef __AGX_DEVICE_H
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#define __AGX_DEVICE_H
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#include "util/simple_mtx.h"
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#include "util/sparse_array.h"
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#include "util/vma.h"
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#include "agx_bo.h"
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#include "agx_formats.h"
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enum agx_dbg {
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AGX_DBG_TRACE = BITFIELD_BIT(0),
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AGX_DBG_DEQP = BITFIELD_BIT(1),
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AGX_DBG_NO16 = BITFIELD_BIT(2),
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AGX_DBG_DIRTY = BITFIELD_BIT(3),
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AGX_DBG_PRECOMPILE = BITFIELD_BIT(4),
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AGX_DBG_PERF = BITFIELD_BIT(5),
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AGX_DBG_NOCOMPRESS = BITFIELD_BIT(6),
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AGX_DBG_NOCLUSTER = BITFIELD_BIT(7),
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AGX_DBG_SYNC = BITFIELD_BIT(8),
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AGX_DBG_STATS = BITFIELD_BIT(9),
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AGX_DBG_RESOURCE = BITFIELD_BIT(10),
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AGX_DBG_BATCH = BITFIELD_BIT(11),
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AGX_DBG_NOWC = BITFIELD_BIT(12),
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AGX_DBG_SYNCTVB = BITFIELD_BIT(13),
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AGX_DBG_SMALLTILE = BITFIELD_BIT(14),
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AGX_DBG_NOMSAA = BITFIELD_BIT(15),
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AGX_DBG_NOSHADOW = BITFIELD_BIT(16),
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};
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/* Dummy partial declarations, pending real UAPI */
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enum drm_asahi_cmd_type { DRM_ASAHI_CMD_TYPE_PLACEHOLDER_FOR_DOWNSTREAM_UAPI };
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enum drm_asahi_sync_type { DRM_ASAHI_SYNC_SYNCOBJ };
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struct drm_asahi_sync {
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uint32_t sync_type;
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uint32_t handle;
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};
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struct drm_asahi_params_global {
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uint64_t vm_page_size;
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uint64_t vm_user_start;
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uint64_t vm_user_end;
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uint64_t vm_shader_start;
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uint64_t vm_shader_end;
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uint32_t chip_id;
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uint32_t num_clusters_total;
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uint32_t gpu_generation;
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uint32_t gpu_variant;
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uint32_t num_dies;
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};
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/* How many power-of-two levels in the BO cache do we want? 2^14 minimum chosen
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* as it is the page size that all allocations are rounded to
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*/
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#define MIN_BO_CACHE_BUCKET (14) /* 2^14 = 16KB */
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#define MAX_BO_CACHE_BUCKET (22) /* 2^22 = 4MB */
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/* Fencepost problem, hence the off-by-one */
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#define NR_BO_CACHE_BUCKETS (MAX_BO_CACHE_BUCKET - MIN_BO_CACHE_BUCKET + 1)
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/* Forward decl only, do not pull in all of NIR */
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struct nir_shader;
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struct agx_device {
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uint32_t debug;
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/* NIR library of AGX helpers/shaders. Immutable once created. */
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const struct nir_shader *libagx;
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char name[64];
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struct drm_asahi_params_global params;
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uint64_t next_global_id, last_global_id;
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/* Device handle */
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int fd;
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/* VM handle */
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uint32_t vm_id;
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/* Queue handle */
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uint32_t queue_id;
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/* VMA heaps */
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simple_mtx_t vma_lock;
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uint64_t shader_base;
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struct util_vma_heap main_heap;
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struct util_vma_heap usc_heap;
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uint64_t guard_size;
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struct renderonly *ro;
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pthread_mutex_t bo_map_lock;
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struct util_sparse_array bo_map;
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uint32_t max_handle;
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struct {
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simple_mtx_t lock;
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/* List containing all cached BOs sorted in LRU (Least Recently Used)
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* order so we can quickly evict BOs that are more than 1 second old.
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*/
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struct list_head lru;
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/* The BO cache is a set of buckets with power-of-two sizes. Each bucket
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* is a linked list of free panfrost_bo objects.
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*/
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struct list_head buckets[NR_BO_CACHE_BUCKETS];
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/* Current size of the BO cache in bytes (sum of sizes of cached BOs) */
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size_t size;
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/* Number of hits/misses for the BO cache */
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uint64_t hits, misses;
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} bo_cache;
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};
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bool agx_open_device(void *memctx, struct agx_device *dev);
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void agx_close_device(struct agx_device *dev);
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static inline struct agx_bo *
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agx_lookup_bo(struct agx_device *dev, uint32_t handle)
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{
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return util_sparse_array_get(&dev->bo_map, handle);
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}
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void agx_bo_mmap(struct agx_bo *bo);
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uint64_t agx_get_global_id(struct agx_device *dev);
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uint32_t agx_create_command_queue(struct agx_device *dev, uint32_t caps);
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int agx_submit_single(struct agx_device *dev, enum drm_asahi_cmd_type cmd_type,
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uint32_t barriers, struct drm_asahi_sync *in_syncs,
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unsigned in_sync_count, struct drm_asahi_sync *out_syncs,
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unsigned out_sync_count, void *cmdbuf,
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uint32_t result_handle, uint32_t result_off,
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uint32_t result_size);
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int agx_import_sync_file(struct agx_device *dev, struct agx_bo *bo, int fd);
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int agx_export_sync_file(struct agx_device *dev, struct agx_bo *bo);
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void agx_debug_fault(struct agx_device *dev, uint64_t addr);
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#endif
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