mesa/src
Alyssa Rosenzweig ee7aaa27b8 pan/bi: Implement spilling at the clause-level
We use essentially the same logic, but we need to treat entire clauses
as large instructions, and spill on clause boundaries instead of
instruction boundaries. So factor out the code a bit, using the new
iterators, removing bi_unwrap_singleton.

A few specific fixes are needed to adapt. One is simple: rewriting
destinations needs to preserve clamps and such. The other is a much more
subtle bug. Consider the clause

   {
      ADD 0, ...
      ---unrelated code---
      MUL 1, 0, ...
   }

Suppose we spill 0. The naive spill code would generate an SSA temporary to
spill to and another SSA temporary to fill from, generating:

   {
      LOAD.tl 10
   }
   {
      ADD 11, ...
      ---unrelated code---
      MUL 1, 10, ...
   }
   {
      STORE.tl 11
   }

But this is wrong; the MUL now reads stale (and for SSA, likely
undefined/uninitialized) data. The simplest fix, employed here, is to
spill/fill within a clause simultaneously, which means the temporary
can't be SSA, generating correct code:

   {
      LOAD.tl r0
   }
   {
      ADD r0, ...
      ---unrelated code---
      MUL 1, r0, ...
   }
   {
      STORE.tl r0
   }

This is suboptimal, since the LOAD is still likely reading garbage that
is unused. But it is still correct, and the next commit will avoid
generating the load in this case.

To make the bug even more subtle, if ADD/MUL are within 2-3 instructions
of each other, the scheduler will optimize the load to a
temporary/passthrough, so the bug isn't noticed. It only happens if they
are 3+ instructions apart yet still in the same clause (<=16
instructions).

Special thanks to macc24 for reporting this bug and to Jason Ekstrand
for allowing me to rubberduck.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
2021-01-29 16:55:43 +00:00
..
amd radv: fix centroid with VRS coarse shading 2021-01-29 12:53:15 +00:00
android_stub egl/android: implement image cleanup callback 2020-12-15 06:05:27 +00:00
broadcom vc4: add drm-shim 2021-01-28 16:14:06 +00:00
compiler meson: add enable-glcpp-tests option 2021-01-28 15:52:32 +00:00
drm-shim drm-shim: Fix unused variable warnings from asserts in release build. 2020-08-28 22:45:08 +00:00
egl egl/dri2: enable EGL_WL_bind_wayland_display in EGL device platform 2021-01-28 00:30:10 +00:00
etnaviv etnaviv, v3d: Fix valgrind include paths. 2020-12-15 19:39:29 +00:00
freedreno ir3: Assume that nir_tex_instr::dest_type is sized 2021-01-25 11:22:07 +01:00
gallium panfrost: Allow waiting on slots 6/7 during preload 2021-01-29 16:55:43 +00:00
gbm egl: implement EGL_EXT_protected_surface support 2020-11-02 10:15:47 +01:00
getopt
glx glx: Provide glvnd wrapper for glXSwapIntervalEXT 2021-01-22 22:34:23 -08:00
gtest
hgl hgl: Major refactor and cleanup 2021-01-09 20:51:35 -06:00
imgui
intel intel/compiler: cache computed register pressure benefit 2021-01-29 11:31:39 +00:00
loader loader: Print dlerror() output in the failure message 2020-11-04 21:45:37 +00:00
mapi glapi: guard against invalid XML definitions for glthread 2021-01-29 02:28:42 +00:00
mesa glthread: fix interpreting vertex size == GL_BGRA for vertex attribs 2021-01-29 02:28:42 +00:00
microsoft microsoft: Fix comma in variadic macro for MSVC 2021-01-29 05:43:31 +00:00
nouveau nouveau: add drm-shim support 2021-01-11 22:45:01 +00:00
panfrost pan/bi: Implement spilling at the clause-level 2021-01-29 16:55:43 +00:00
util util: Use explicit relaxed reads for u_queue 2021-01-28 18:07:09 +00:00
virtio virgl: update headers 2021-01-22 21:25:48 +00:00
vulkan vulkan: Update XML and headers to 1.2.168 2021-01-27 22:20:52 +00:00
meson.build nouveau: add drm-shim support 2021-01-11 22:45:01 +00:00
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