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1e0fe81b69
not planning to work on the TODOs immediately Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38385>
114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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/* Common Subexpression Elimination
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*
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* This implementation behaves more like Global Value Numbering (GVN) than
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* traditional CSE. While traditional CSE eliminates redundant instructions
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* that have identical representations, GVN eliminates redundant instructions
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* that have identical behavior.
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*
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* The pass walks the shader and adds instructions into a set whose equality
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* function returns whether the behavior of 2 instructions is identical.
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* When we encounter an instruction that is already in the set, the instruction
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* is eliminated if the instruction in the set dominates it, else
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* the instruction replaces the instruction in the set (see example 4).
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*
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* Non-reorderable intrinsics are ignored with the exception of certain
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* non-reorderable subgroups ops and intrinsics like demote and terminate that
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* are CSE'd.
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*
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* Example 1. Identical instructions:
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* %2 = iadd %0, %1
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* control_flow {
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* %3 = iadd %0, %1 // eliminated
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* }
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*
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* Example 2. Commutative instructions:
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* %3 = ffma %0, %1, %2
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* %4 = ffma %1, %0, %2 // eliminated
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*
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* Example 3. Non-matching ALU flags are merged:
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* %2 = fmul %0, %1 (fp_fast_math) // exact added here
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* %3 = fmul %0, %1 (exact) // eliminated
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*
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* Example 4. Non-dominating situation:
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* if {
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* %2 = iadd %0, %1
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* } else {
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* %3 = iadd %0, %1 // keep, but replace %2 in the set
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* %4 = iadd %0, %1 // eliminated
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* }
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* TODO: We could move %2 before "if" in this pass instead. It would also
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* reduce register usage when %0 and %1 are no longer live in
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* the range between "if" and %3, while only %2 would be live in that
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* range.
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*
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* TODO - everything below is not implemented:
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*
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* Implementing the following cases could eliminate most of nir_opt_copy_prop:
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*
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* Case 1. Copy propagation of movs without swizzles:
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* 32x4 %2 = (any instruction)
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* 32x4 %3 = mov %2.xyzw // eliminated since it's equal to %2
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*
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* Case 2. Copy propagation of movs with swizzles:
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* 32x2 %2 = (any instruction)
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* 32x3 %3 = mov %2.yxx // eliminated conditionally
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* All %3 uses that are ALU will absorb the swizzle and are changed
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* to use %2, and those uses that are not ALU will keep the mov.
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*
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* While vecN is possible to occur here instead, NIR should always create
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* swizzled mov instead of vecN when all components use the same def, and
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* nir_validate should assert that, so this should never occur:
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* 32x4 %2 = vec4 %1.?, %1.?, %1.?, %1.?
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*/
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#include "nir.h"
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#include "nir_instr_set.h"
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static bool
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dominates(const nir_instr *old_instr, const nir_instr *new_instr)
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{
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return nir_block_dominates(old_instr->block, new_instr->block);
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}
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static bool
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nir_opt_cse_impl(nir_function_impl *impl)
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{
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struct set instr_set;
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nir_instr_set_init(&instr_set, NULL);
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_mesa_set_resize(&instr_set, impl->ssa_alloc);
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nir_metadata_require(impl, nir_metadata_dominance);
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bool progress = false;
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (nir_instr_set_add_or_rewrite(&instr_set, instr, dominates)) {
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progress = true;
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nir_instr_remove(instr);
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}
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}
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}
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nir_progress(progress, impl, nir_metadata_control_flow);
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nir_instr_set_fini(&instr_set);
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return progress;
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}
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bool
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nir_opt_cse(nir_shader *shader)
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{
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bool progress = false;
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nir_foreach_function_impl(impl, shader) {
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progress |= nir_opt_cse_impl(impl);
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}
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return progress;
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}
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