mesa/src/gallium/drivers
Christian Gmeiner 96c99bc2d9 etnaviv: linker: add fallback lookup to VARYING_SLOT_BFC[n]
There are valid NIR shaders pairs where the vertex shader has
a VARYING_SLOT_BFC0 shader_out and the corresponding framgent
shader has a VARYING_SLOT_COL0 shader_in.
So at link time if there is no matching VARYING_SLOT_BFC[n],
we must map VARYING_SLOT_BFC0[n] to VARYING_SLOT_COL[n].

Example shader pair from 'spec@!opengl 2.0@vertex-program-two-side back':

shader: MESA_SHADER_VERTEX
source_sha1: {0xf916f77d, 0xffa6ab5e, 0x160976a7, 0xb59fe59c, 0x92e8f3f6}
name: GLSL3
internal: false
stage: 0
next_stage: 4
inputs_read: 0
outputs_written: 0,13
subgroup_size: 1
bit_sizes_float: 0x20
bit_sizes_int: 0x20
first_ubo_is_default_ubo: true
flrp_lowered: true
inputs: 1
outputs: 2
uniforms: 0
decl_var shader_in INTERP_MODE_NONE vec4 gl_Vertex (VERT_ATTRIB_POS.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_BackColor (VARYING_SLOT_BFC0.xyzw, 1, 0)
decl_function main (0 params)

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = deref_var &gl_Vertex (shader_in vec4)
        vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0)
        vec4 32 ssa_2 = load_const (0x00000000, 0x00000000, 0x3f000000, 0x00000000) = (0.000000, 0.000000, 0.500000, 0.000000)
        vec1 32 ssa_5 = deref_var &gl_BackColor (shader_out vec4)
        vec4 32 ssa_11 = mov ssa_2
        vec4 32 ssa_13 = fsat ssa_11
        intrinsic store_deref (ssa_5, ssa_13) (wrmask=xyzw, access=0)
        vec1 32 ssa_7 = deref_var &gl_Position (shader_out vec4)
        vec4 32 ssa_12 = mov ssa_1
        intrinsic store_deref (ssa_7, ssa_12) (wrmask=xyzw, access=0)
        /* succs: block_1 */
        block block_1:
}

shader: MESA_SHADER_FRAGMENT
source_sha1: {0x5059da66, 0x00c609e5, 0x5329c39a, 0x13e2fc88, 0x8e68cb71}
name: GLSL3
internal: false
stage: 4
next_stage: 4
inputs_read: 1
outputs_written: 2
subgroup_size: 1
first_ubo_is_default_ubo: true
flrp_lowered: true
inputs: 1
outputs: 1
uniforms: 0
decl_var shader_in INTERP_MODE_NONE vec4 gl_Color (VARYING_SLOT_COL0.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0)
decl_function main (0 params)

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = deref_var &gl_Color (shader_in vec4)
        vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0)
        vec1 32 ssa_2 = deref_var &gl_FragColor (shader_out vec4)
        intrinsic store_deref (ssa_2, ssa_1) (wrmask=xyzw, access=0)
        /* succs: block_1 */
        block block_1:
}

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23850>
2023-06-27 09:26:40 +00:00
..
asahi asahi: Pass through surface sample count 2023-06-23 17:37:41 +00:00
crocus crocus/screen: add PIPE_CAP_TIMER_RESOLUTION 2023-06-22 09:08:33 +00:00
d3d12 nir: add and use nir_imod_imm 2023-06-15 13:34:49 +00:00
etnaviv etnaviv: linker: add fallback lookup to VARYING_SLOT_BFC[n] 2023-06-27 09:26:40 +00:00
freedreno compiler: Move spirv into a module of its own 2023-06-20 16:18:08 +00:00
i915 treewide: Remove use_scoped_barrier 2023-06-13 16:36:10 +00:00
iris intel/ds: Track CCS cache flush bit 2023-06-26 16:08:20 -07:00
lima gallium: Drop PIPE_SHADER_CAP_PREFERRED_IR. 2023-06-12 17:37:54 +00:00
llvmpipe llvmpipe/screen: add PIPE_CAP_TIMER_RESOLUTION 2023-06-22 09:08:33 +00:00
nouveau nvc0: fix printing shaders 2023-06-24 02:12:14 +00:00
panfrost gallium: Drop PIPE_SHADER_CAP_PREFERRED_IR. 2023-06-12 17:37:54 +00:00
r300 r300: properly count maximum used register index 2023-06-24 11:30:47 +00:00
r600 nir/lower_locals_to_regs: Add bool bitsize knob 2023-06-26 08:22:06 -04:00
radeonsi radeonsi: Remove unconditional POPS_DRAIN_PS_ON_OVERLAP setting 2023-06-26 15:58:04 +00:00
softpipe sofpipe/screen: add PIPE_CAP_TIMER_RESOLUTION 2023-06-22 09:08:33 +00:00
svga gallium: Remove unused os_process.h in gallium/auxiliary 2023-06-20 05:02:51 +00:00
tegra treewide: use uint64_t / (u)intptr_t in image address calculations 2023-06-07 16:53:36 +00:00
v3d v3d: clear alpha-only as red-only 2023-06-20 07:45:31 +00:00
vc4 gallium: Drop PIPE_SHADER_CAP_PREFERRED_IR. 2023-06-12 17:37:54 +00:00
virgl ci: Upref virglrenderer 2023-06-23 10:00:49 +00:00
zink zink/ci: Add broken fragment shader interlock test to RADV flakes 2023-06-26 15:58:04 +00:00