Leo Liu e560a11b87 radeon/vce: increase cpb height alignment ... Height should be aligned with 2 macroblocks, thus making safer for tiled mode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>		2016-07-05 09:15:47 -04:00
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compiler	glsl: stop allocating memory for UBOs during linking	2016-07-05 20:18:05 +10:00
egl	Added pbuffer hooks for surfaceless platform	2016-06-14 08:51:02 -07:00
gallium	radeon/vce: increase cpb height alignment	2016-07-05 09:15:47 -04:00
gbm	gbm: Fix comments	2016-06-23 13:55:03 -07:00
getopt
glx	Remove wrongly repeated words in comments	2016-06-23 13:55:03 -07:00
gtest	Remove wrongly repeated words in comments	2016-06-23 13:55:03 -07:00
hgl
intel	anv: automake: indent with tabs and not spaces	2016-07-05 12:16:06 +01:00
loader	Android: move libdrm settings to top-level Android.common.mk	2016-06-13 15:31:29 +01:00
mapi	mapi: Export all GLES 3.1 functions in libGLESv2.so	2016-06-29 14:28:59 -07:00
mesa	i965: Remove trailing whitespace	2016-07-05 14:06:37 +02:00
util	mesa/gallium: Move u_bit_scan{,64} from gallium to util.	2016-06-14 05:19:10 +02:00
Makefile.am	automake: don't mandate git_sha1.h/MESA_GIT_SHA1	2016-07-05 12:16:20 +01:00
SConscript	scons: put the generated git_sha1.h file in top-level src/ directory	2016-06-17 10:33:00 -06:00