Rohan Garg e1289d6135 intel/compiler: Adjust CS payload registers for new register width on Xe2+ ... Signed-off-by: Rohan Garg <rohan.garg@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>		2023-09-20 17:19:36 -07:00
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blorp	blorp: fix hangs with mesh enabled	2023-09-12 02:51:31 +00:00
ci	ci/intel: Add various updates from our nightly runs.	2023-09-19 22:50:07 +00:00
common	intel/common: Add sse2_args for 32-bit build when -Dsse2=false was set	2023-09-15 17:39:55 -07:00
compiler	intel/compiler: Adjust CS payload registers for new register width on Xe2+	2023-09-20 17:19:36 -07:00
dev	intel: Sync xe_drm.h	2023-09-13 16:38:15 +00:00
ds	intel/compiler,intel/blorp,intel/vulkan: decouple vulkan driver and compiler from gallium	2023-08-03 22:00:15 +00:00
genxml	intel/genxml: Auto-import genxml files using genxml_import.py	2023-09-14 11:05:16 -07:00
isl	isl/tilememcpy_test: add multiple tile testing	2023-09-02 21:49:05 -07:00
nullhw-layer	meson: support installation tags	2023-09-11 13:00:45 +00:00
perf	intel: Move i915_drm.h specific code from common/intel_gem.h to common/i915/intel_gem.h	2023-07-28 15:36:52 +00:00
tools	intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c	2023-09-06 01:39:53 +00:00
vulkan	anv: refactor to fix pipe control debugging	2023-09-20 06:04:37 +00:00
vulkan_hasvk	treewide: Drop nir_ssa_for_src users	2023-09-18 10:25:17 -04:00
meson.build	intel: Only build perf if drivers or tools are enabled	2023-08-31 21:53:19 +00:00