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30521fb19e
This is not really a cache yet, but it allows us to share one state stream for all pipelines, which means we can bump the block size without wasting a lot of memory.
532 lines
23 KiB
C
532 lines
23 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "gen7_pack.h"
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#include "gen75_pack.h"
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#include "genX_pipeline_util.h"
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static void
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emit_vertex_input(struct anv_pipeline *pipeline,
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const VkPipelineVertexInputStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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uint32_t elements;
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if (extra && extra->disable_vs) {
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/* If the VS is disabled, just assume the user knows what they're
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* doing and apply the layout blindly. This can only come from
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* meta, so this *should* be safe.
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*/
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elements = 0;
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
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elements |= (1 << info->pVertexAttributeDescriptions[i].location);
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} else {
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/* Pull inputs_read out of the VS prog data */
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uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
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assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
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elements = inputs_read >> VERT_ATTRIB_GENERIC0;
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}
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uint32_t vb_count = __builtin_popcount(elements);
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if (pipeline->vs_prog_data.uses_vertexid ||
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pipeline->vs_prog_data.uses_instanceid)
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vb_count++;
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if (vb_count == 0)
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return;
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const uint32_t num_dwords = 1 + vb_count * 2;
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uint32_t *p = anv_batch_emitn(&pipeline->batch, num_dwords,
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GEN7_3DSTATE_VERTEX_ELEMENTS);
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memset(p + 1, 0, (num_dwords - 1) * 4);
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
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const VkVertexInputAttributeDescription *desc =
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&info->pVertexAttributeDescriptions[i];
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enum isl_format format = anv_get_isl_format(desc->format,
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VK_IMAGE_ASPECT_COLOR_BIT,
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VK_IMAGE_TILING_LINEAR);
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assert(desc->binding < 32);
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if ((elements & (1 << desc->location)) == 0)
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continue; /* Binding unused */
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uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
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struct GEN7_VERTEX_ELEMENT_STATE element = {
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.VertexBufferIndex = desc->binding,
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.Valid = true,
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.SourceElementFormat = format,
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.EdgeFlagEnable = false,
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.SourceElementOffset = desc->offset,
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.Component0Control = vertex_element_comp_control(format, 0),
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.Component1Control = vertex_element_comp_control(format, 1),
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.Component2Control = vertex_element_comp_control(format, 2),
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.Component3Control = vertex_element_comp_control(format, 3),
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};
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GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + slot * 2], &element);
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}
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if (pipeline->vs_prog_data.uses_vertexid ||
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pipeline->vs_prog_data.uses_instanceid) {
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struct GEN7_VERTEX_ELEMENT_STATE element = {
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.Valid = true,
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/* FIXME: Do we need to provide the base vertex as component 0 here
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* to support the correct base vertex ID? */
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.Component0Control = VFCOMP_STORE_0,
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.Component1Control = VFCOMP_STORE_0,
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.Component2Control = VFCOMP_STORE_VID,
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.Component3Control = VFCOMP_STORE_IID
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};
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GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + (vb_count - 1) * 2], &element);
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}
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}
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static void
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gen7_emit_rs_state(struct anv_pipeline *pipeline,
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const VkPipelineRasterizationStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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struct GEN7_3DSTATE_SF sf = {
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GEN7_3DSTATE_SF_header,
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/* FIXME: Get this from pass info */
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.DepthBufferSurfaceFormat = D24_UNORM_X8_UINT,
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/* LegacyGlobalDepthBiasEnable */
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.StatisticsEnable = true,
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.FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
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.BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
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.ViewTransformEnable = !(extra && extra->disable_viewport),
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.FrontWinding = vk_to_gen_front_face[info->frontFace],
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/* bool AntiAliasingEnable; */
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.CullMode = vk_to_gen_cullmode[info->cullMode],
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/* uint32_t LineEndCapAntialiasingRegionWidth; */
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.ScissorRectangleEnable = !(extra && extra->disable_scissor),
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/* uint32_t MultisampleRasterizationMode; */
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/* bool LastPixelEnable; */
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.TriangleStripListProvokingVertexSelect = 0,
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.LineStripListProvokingVertexSelect = 0,
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.TriangleFanProvokingVertexSelect = 0,
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/* uint32_t AALineDistanceMode; */
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/* uint32_t VertexSubPixelPrecisionSelect; */
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.UsePointWidthState = !pipeline->writes_point_size,
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.PointWidth = 1.0,
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};
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GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
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}
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static void
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gen7_emit_ds_state(struct anv_pipeline *pipeline,
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const VkPipelineDepthStencilStateCreateInfo *info)
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{
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if (info == NULL) {
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/* We're going to OR this together with the dynamic state. We need
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* to make sure it's initialized to something useful.
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*/
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memset(pipeline->gen7.depth_stencil_state, 0,
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sizeof(pipeline->gen7.depth_stencil_state));
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return;
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}
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struct GEN7_DEPTH_STENCIL_STATE state = {
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.DepthTestEnable = info->depthTestEnable,
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.DepthBufferWriteEnable = info->depthWriteEnable,
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.DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
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.DoubleSidedStencilEnable = true,
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.StencilTestEnable = info->stencilTestEnable,
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.StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
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.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
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.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
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.StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
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.BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
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.BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
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.BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
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.BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
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};
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GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
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}
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static void
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gen7_emit_cb_state(struct anv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *info,
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const VkPipelineMultisampleStateCreateInfo *ms_info)
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{
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struct anv_device *device = pipeline->device;
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if (info->pAttachments == NULL) {
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pipeline->blend_state =
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anv_state_pool_emit(&device->dynamic_state_pool,
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GEN7_BLEND_STATE, 64,
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.ColorBufferBlendEnable = false,
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.WriteDisableAlpha = false,
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.WriteDisableRed = false,
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.WriteDisableGreen = false,
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.WriteDisableBlue = false);
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} else {
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/* FIXME-GEN7: All render targets share blend state settings on gen7, we
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* can't implement this.
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*/
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const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
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pipeline->blend_state =
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anv_state_pool_emit(&device->dynamic_state_pool,
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GEN7_BLEND_STATE, 64,
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.ColorBufferBlendEnable = a->blendEnable,
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.IndependentAlphaBlendEnable = true, /* FIXME: yes? */
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.AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
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.SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
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.DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
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.ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
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.SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
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.DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
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.AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
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# if 0
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bool AlphaToOneEnable;
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bool AlphaToCoverageDitherEnable;
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# endif
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.WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
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.WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
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.WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
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.WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
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.LogicOpEnable = info->logicOpEnable,
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.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
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# if 0
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bool AlphaTestEnable;
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uint32_t AlphaTestFunction;
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bool ColorDitherEnable;
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uint32_t XDitherOffset;
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uint32_t YDitherOffset;
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uint32_t ColorClampRange;
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bool PreBlendColorClampEnable;
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bool PostBlendColorClampEnable;
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# endif
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);
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}
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
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.BlendStatePointer = pipeline->blend_state.offset);
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}
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static inline uint32_t
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scratch_space(const struct brw_stage_prog_data *prog_data)
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{
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return ffs(prog_data->total_scratch / 1024);
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}
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GENX_FUNC(GEN7, GEN75) VkResult
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genX(graphics_pipeline_create)(
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VkDevice _device,
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struct anv_pipeline_cache * cache,
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const VkGraphicsPipelineCreateInfo* pCreateInfo,
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const struct anv_graphics_pipeline_create_info *extra,
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const VkAllocationCallbacks* pAllocator,
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VkPipeline* pPipeline)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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struct anv_pipeline *pipeline;
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VkResult result;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
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pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (pipeline == NULL)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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result = anv_pipeline_init(pipeline, device, cache,
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pCreateInfo, extra, pAllocator);
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if (result != VK_SUCCESS) {
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anv_free2(&device->alloc, pAllocator, pipeline);
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return result;
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}
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assert(pCreateInfo->pVertexInputState);
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emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
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assert(pCreateInfo->pRasterizationState);
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gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
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gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
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gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
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pCreateInfo->pMultisampleState);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
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.StatisticsEnable = true);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
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/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
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*
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* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
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* needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
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* 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
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* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
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* needs to be sent before any combination of VS associated 3DSTATE."
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*/
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anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
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.DepthStallEnable = true,
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.PostSyncOperation = WriteImmediateData,
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.Address = { &device->workaround_bo, 0 });
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
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.ConstantBufferOffset = 0,
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.ConstantBufferSize = 4);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
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.ConstantBufferOffset = 4,
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.ConstantBufferSize = 4);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
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.ConstantBufferOffset = 8,
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.ConstantBufferSize = 4);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
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const VkPipelineRasterizationStateCreateInfo *rs_info =
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pCreateInfo->pRasterizationState;
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
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.FrontWinding = vk_to_gen_front_face[rs_info->frontFace],
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.CullMode = vk_to_gen_cullmode[rs_info->cullMode],
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.ClipEnable = true,
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.APIMode = APIMODE_OGL,
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.ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
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.ClipMode = CLIPMODE_NORMAL,
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.TriangleStripListProvokingVertexSelect = 0,
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.LineStripListProvokingVertexSelect = 0,
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.TriangleFanProvokingVertexSelect = 0,
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.MinimumPointWidth = 0.125,
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.MaximumPointWidth = 255.875);
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uint32_t samples = 1;
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uint32_t log2_samples = __builtin_ffs(samples) - 1;
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
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.PixelLocation = PIXLOC_CENTER,
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.NumberofMultisamples = log2_samples);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
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.SampleMask = 0xff);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
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.VSURBStartingAddress = pipeline->urb.vs_start,
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.VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
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.VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
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.GSURBStartingAddress = pipeline->urb.gs_start,
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.GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
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.GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
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.HSURBStartingAddress = pipeline->urb.vs_start,
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.HSURBEntryAllocationSize = 0,
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.HSNumberofURBEntries = 0);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
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.DSURBStartingAddress = pipeline->urb.vs_start,
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.DSURBEntryAllocationSize = 0,
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.DSNumberofURBEntries = 0);
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const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
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/* The last geometry producing stage will set urb_offset and urb_length,
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* which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
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uint32_t urb_offset = 1;
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uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
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#if 0
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/* From gen7_vs_state.c */
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/**
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* From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
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* Geometry > Geometry Shader > State:
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*
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* "Note: Because of corruption in IVB:GT2, software needs to flush the
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* whole fixed function pipeline when the GS enable changes value in
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* the 3DSTATE_GS."
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*
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* The hardware architects have clarified that in this context "flush the
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* whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
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* Stall" bit set.
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*/
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if (!brw->is_haswell && !brw->is_baytrail)
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gen7_emit_vs_workaround_flush(brw);
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#endif
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if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
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else
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
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.KernelStartPointer = pipeline->vs_vec4,
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.ScratchSpaceBaseOffset = pipeline->scratch_start[MESA_SHADER_VERTEX],
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.PerThreadScratchSpace = scratch_space(&vue_prog_data->base),
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.DispatchGRFStartRegisterforURBData =
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vue_prog_data->base.dispatch_grf_start_reg,
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.VertexURBEntryReadLength = vue_prog_data->urb_read_length,
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.VertexURBEntryReadOffset = 0,
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.MaximumNumberofThreads = device->info.max_vs_threads - 1,
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.StatisticsEnable = true,
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.VSFunctionEnable = true);
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const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
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if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
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} else {
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urb_offset = 1;
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urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
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|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
|
|
.KernelStartPointer = pipeline->gs_kernel,
|
|
.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
|
|
.PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base),
|
|
|
|
.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
|
|
.OutputTopology = gs_prog_data->output_topology,
|
|
.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
|
|
.IncludeVertexHandles = gs_prog_data->base.include_vue_handles,
|
|
.DispatchGRFStartRegisterforURBData =
|
|
gs_prog_data->base.base.dispatch_grf_start_reg,
|
|
|
|
.MaximumNumberofThreads = device->info.max_gs_threads - 1,
|
|
/* This in the next dword on HSW. */
|
|
.ControlDataFormat = gs_prog_data->control_data_format,
|
|
.ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
|
|
.InstanceControl = MAX2(gs_prog_data->invocations, 1) - 1,
|
|
.DispatchMode = gs_prog_data->base.dispatch_mode,
|
|
.GSStatisticsEnable = true,
|
|
.IncludePrimitiveID = gs_prog_data->include_primitive_id,
|
|
# if (ANV_IS_HASWELL)
|
|
.ReorderMode = REORDER_TRAILING,
|
|
# else
|
|
.ReorderEnable = true,
|
|
# endif
|
|
.GSEnable = true);
|
|
}
|
|
|
|
const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
|
|
if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
|
|
wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
|
|
anv_finishme("two-sided color needs sbe swizzling setup");
|
|
if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
|
|
anv_finishme("primitive_id needs sbe swizzling setup");
|
|
|
|
/* FIXME: generated header doesn't emit attr swizzle fields */
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
|
|
.NumberofSFOutputAttributes = pipeline->wm_prog_data.num_varying_inputs,
|
|
.VertexURBEntryReadLength = urb_length,
|
|
.VertexURBEntryReadOffset = urb_offset,
|
|
.PointSpriteTextureCoordinateOrigin = UPPERLEFT);
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
|
|
.KernelStartPointer0 = pipeline->ps_ksp0,
|
|
.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
|
|
.PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
|
|
|
|
.MaximumNumberofThreads = device->info.max_wm_threads - 1,
|
|
.PushConstantEnable = wm_prog_data->base.nr_params > 0,
|
|
.AttributeEnable = wm_prog_data->num_varying_inputs > 0,
|
|
.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
|
|
|
|
.RenderTargetFastClearEnable = false,
|
|
.DualSourceBlendEnable = false,
|
|
.RenderTargetResolveEnable = false,
|
|
|
|
.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
|
|
POSOFFSET_SAMPLE : POSOFFSET_NONE,
|
|
|
|
._32PixelDispatchEnable = false,
|
|
._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
|
|
._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
|
|
|
|
.DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
|
|
.DispatchGRFStartRegisterforConstantSetupData1 = 0,
|
|
.DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
|
|
|
|
#if 0
|
|
/* Haswell requires the sample mask to be set in this packet as well as
|
|
* in 3DSTATE_SAMPLE_MASK; the values should match. */
|
|
/* _NEW_BUFFERS, _NEW_MULTISAMPLE */
|
|
#endif
|
|
|
|
.KernelStartPointer1 = 0,
|
|
.KernelStartPointer2 = pipeline->ps_ksp2);
|
|
|
|
/* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
|
|
.StatisticsEnable = true,
|
|
.ThreadDispatchEnable = true,
|
|
.LineEndCapAntialiasingRegionWidth = 0, /* 0.5 pixels */
|
|
.LineAntialiasingRegionWidth = 1, /* 1.0 pixels */
|
|
.EarlyDepthStencilControl = EDSC_NORMAL,
|
|
.PointRasterizationRule = RASTRULE_UPPER_RIGHT,
|
|
.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
|
|
.BarycentricInterpolationMode = wm_prog_data->barycentric_interp_modes);
|
|
|
|
*pPipeline = anv_pipeline_to_handle(pipeline);
|
|
|
|
return VK_SUCCESS;
|
|
}
|
|
|
|
GENX_FUNC(GEN7, GEN75) VkResult
|
|
genX(compute_pipeline_create)(
|
|
VkDevice _device,
|
|
struct anv_pipeline_cache * cache,
|
|
const VkComputePipelineCreateInfo* pCreateInfo,
|
|
const VkAllocationCallbacks* pAllocator,
|
|
VkPipeline* pPipeline)
|
|
{
|
|
anv_finishme("primitive_id needs sbe swizzling setup");
|
|
abort();
|
|
}
|