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https://gitlab.freedesktop.org/mesa/mesa.git
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df645fa369
This actually supports more of the extension than the LLVM backend but we can't enable it because ACO doesn't work with all stages yet. With more of it enabled, some CTS tests fail because our 64-bit sqrt is very imprecise. I can't find any precision requirements for it anywhere, so I'm thinking it might be a CTS issue. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
383 lines
14 KiB
C++
383 lines
14 KiB
C++
/*
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* Copyright © 2018 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <map>
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#include <unordered_map>
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#include "aco_ir.h"
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/*
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* Implements the algorithm for dominator-tree value numbering
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* from "Value Numbering" by Briggs, Cooper, and Simpson.
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*/
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namespace aco {
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namespace {
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struct InstrHash {
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std::size_t operator()(Instruction* instr) const
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{
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uint64_t hash = (uint64_t) instr->opcode + (uint64_t) instr->format;
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for (unsigned i = 0; i < instr->operands.size(); i++) {
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Operand op = instr->operands[i];
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uint64_t val = op.isTemp() ? op.tempId() : op.isFixed() ? op.physReg() : op.constantValue();
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hash |= val << (i+1) * 8;
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}
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if (instr->isVOP3()) {
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VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(instr);
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for (unsigned i = 0; i < 3; i++) {
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hash ^= vop3->abs[i] << (i*3 + 0);
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hash ^= vop3->opsel[i] << (i*3 + 1);
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hash ^= vop3->neg[i] << (i*3 + 2);
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}
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hash ^= (vop3->clamp << 28) * 13;
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hash += vop3->omod << 19;
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}
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switch (instr->format) {
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case Format::SMEM:
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break;
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case Format::VINTRP: {
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Interp_instruction* interp = static_cast<Interp_instruction*>(instr);
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hash ^= interp->attribute << 13;
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hash ^= interp->component << 27;
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break;
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}
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case Format::DS:
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break;
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default:
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break;
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}
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return hash;
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}
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};
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struct InstrPred {
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bool operator()(Instruction* a, Instruction* b) const
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{
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if (a->format != b->format)
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return false;
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if (a->opcode != b->opcode)
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return false;
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if (a->operands.size() != b->operands.size() || a->definitions.size() != b->definitions.size())
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return false; /* possible with pseudo-instructions */
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for (unsigned i = 0; i < a->operands.size(); i++) {
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if (a->operands[i].isConstant()) {
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if (!b->operands[i].isConstant())
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return false;
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if (a->operands[i].constantValue() != b->operands[i].constantValue())
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return false;
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}
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else if (a->operands[i].isTemp()) {
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if (!b->operands[i].isTemp())
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return false;
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if (a->operands[i].tempId() != b->operands[i].tempId())
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return false;
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}
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else if (a->operands[i].isUndefined() ^ b->operands[i].isUndefined())
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return false;
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if (a->operands[i].isFixed()) {
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if (!b->operands[i].isFixed())
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return false;
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if (a->operands[i].physReg() != b->operands[i].physReg())
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return false;
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if (a->operands[i].physReg() == exec && a->pass_flags != b->pass_flags)
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return false;
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}
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}
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for (unsigned i = 0; i < a->definitions.size(); i++) {
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if (a->definitions[i].isTemp()) {
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if (!b->definitions[i].isTemp())
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return false;
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if (a->definitions[i].regClass() != b->definitions[i].regClass())
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return false;
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}
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if (a->definitions[i].isFixed()) {
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if (!b->definitions[i].isFixed())
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return false;
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if (a->definitions[i].physReg() != b->definitions[i].physReg())
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return false;
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if (a->definitions[i].physReg() == exec)
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return false;
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}
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}
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if (a->opcode == aco_opcode::v_readfirstlane_b32)
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return a->pass_flags == b->pass_flags;
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/* The results of VOPC depend on the exec mask if used for subgroup operations. */
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if ((uint32_t) a->format & (uint32_t) Format::VOPC && a->pass_flags != b->pass_flags)
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return false;
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if (a->format == Format::PSEUDO_BRANCH)
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return false;
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if (a->isVOP3()) {
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VOP3A_instruction* a3 = static_cast<VOP3A_instruction*>(a);
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VOP3A_instruction* b3 = static_cast<VOP3A_instruction*>(b);
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for (unsigned i = 0; i < 3; i++) {
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if (a3->abs[i] != b3->abs[i] ||
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a3->opsel[i] != b3->opsel[i] ||
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a3->neg[i] != b3->neg[i])
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return false;
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}
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return a3->clamp == b3->clamp &&
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a3->omod == b3->omod;
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}
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if (a->isDPP()) {
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DPP_instruction* aDPP = static_cast<DPP_instruction*>(a);
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DPP_instruction* bDPP = static_cast<DPP_instruction*>(b);
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return aDPP->dpp_ctrl == bDPP->dpp_ctrl &&
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aDPP->bank_mask == bDPP->bank_mask &&
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aDPP->row_mask == bDPP->row_mask &&
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aDPP->bound_ctrl == bDPP->bound_ctrl &&
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aDPP->abs[0] == bDPP->abs[0] &&
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aDPP->abs[1] == bDPP->abs[1] &&
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aDPP->neg[0] == bDPP->neg[0] &&
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aDPP->neg[1] == bDPP->neg[1];
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}
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switch (a->format) {
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case Format::SOPK: {
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SOPK_instruction* aK = static_cast<SOPK_instruction*>(a);
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SOPK_instruction* bK = static_cast<SOPK_instruction*>(b);
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return aK->imm == bK->imm;
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}
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case Format::SMEM: {
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SMEM_instruction* aS = static_cast<SMEM_instruction*>(a);
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SMEM_instruction* bS = static_cast<SMEM_instruction*>(b);
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return aS->can_reorder && bS->can_reorder &&
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aS->glc == bS->glc && aS->nv == bS->nv;
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}
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case Format::VINTRP: {
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Interp_instruction* aI = static_cast<Interp_instruction*>(a);
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Interp_instruction* bI = static_cast<Interp_instruction*>(b);
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if (aI->attribute != bI->attribute)
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return false;
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if (aI->component != bI->component)
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return false;
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return true;
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}
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case Format::PSEUDO_REDUCTION: {
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Pseudo_reduction_instruction *aR = static_cast<Pseudo_reduction_instruction*>(a);
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Pseudo_reduction_instruction *bR = static_cast<Pseudo_reduction_instruction*>(b);
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return aR->pass_flags == bR->pass_flags &&
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aR->reduce_op == bR->reduce_op &&
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aR->cluster_size == bR->cluster_size;
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}
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case Format::MTBUF: {
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/* this is fine since they are only used for vertex input fetches */
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MTBUF_instruction* aM = static_cast<MTBUF_instruction *>(a);
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MTBUF_instruction* bM = static_cast<MTBUF_instruction *>(b);
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return aM->can_reorder == bM->can_reorder &&
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aM->barrier == bM->barrier &&
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aM->dfmt == bM->dfmt &&
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aM->nfmt == bM->nfmt &&
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aM->offset == bM->offset &&
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aM->offen == bM->offen &&
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aM->idxen == bM->idxen &&
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aM->glc == bM->glc &&
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aM->slc == bM->slc &&
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aM->tfe == bM->tfe &&
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aM->disable_wqm == bM->disable_wqm;
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}
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/* we want to optimize these in NIR and don't hassle with load-store dependencies */
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case Format::MUBUF:
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case Format::FLAT:
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case Format::GLOBAL:
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case Format::SCRATCH:
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return false;
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case Format::DS: {
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if (a->opcode != aco_opcode::ds_bpermute_b32 &&
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a->opcode != aco_opcode::ds_permute_b32 &&
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a->opcode != aco_opcode::ds_swizzle_b32)
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return false;
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DS_instruction* aD = static_cast<DS_instruction *>(a);
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DS_instruction* bD = static_cast<DS_instruction *>(b);
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return aD->pass_flags == bD->pass_flags &&
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aD->gds == bD->gds &&
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aD->offset0 == bD->offset0 &&
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aD->offset1 == bD->offset1;
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}
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case Format::MIMG: {
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MIMG_instruction* aM = static_cast<MIMG_instruction*>(a);
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MIMG_instruction* bM = static_cast<MIMG_instruction*>(b);
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return aM->can_reorder && bM->can_reorder &&
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aM->barrier == bM->barrier &&
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aM->dmask == bM->dmask &&
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aM->unrm == bM->unrm &&
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aM->glc == bM->glc &&
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aM->slc == bM->slc &&
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aM->tfe == bM->tfe &&
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aM->da == bM->da &&
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aM->lwe == bM->lwe &&
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aM->r128 == bM->r128 &&
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aM->a16 == bM->a16 &&
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aM->d16 == bM->d16 &&
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aM->disable_wqm == bM->disable_wqm;
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}
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default:
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return true;
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}
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}
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};
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using expr_set = std::unordered_map<Instruction*, uint32_t, InstrHash, InstrPred>;
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struct vn_ctx {
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Program* program;
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expr_set expr_values;
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std::map<uint32_t, Temp> renames;
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/* The exec id should be the same on the same level of control flow depth.
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* Together with the check for dominator relations, it is safe to assume
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* that the same exec_id also means the same execution mask.
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* Discards increment the exec_id, so that it won't return to the previous value.
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*/
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uint32_t exec_id = 1;
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vn_ctx(Program* program) : program(program) {}
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};
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bool dominates(vn_ctx& ctx, uint32_t parent, uint32_t child)
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{
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while (parent < child)
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child = ctx.program->blocks[child].logical_idom;
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return parent == child;
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}
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void process_block(vn_ctx& ctx, Block& block)
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{
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std::vector<aco_ptr<Instruction>> new_instructions;
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new_instructions.reserve(block.instructions.size());
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for (aco_ptr<Instruction>& instr : block.instructions) {
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/* first, rename operands */
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for (Operand& op : instr->operands) {
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if (!op.isTemp())
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continue;
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auto it = ctx.renames.find(op.tempId());
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if (it != ctx.renames.end())
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op.setTemp(it->second);
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}
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if (instr->definitions.empty() || instr->opcode == aco_opcode::p_phi || instr->opcode == aco_opcode::p_linear_phi) {
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new_instructions.emplace_back(std::move(instr));
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continue;
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}
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/* simple copy-propagation through renaming */
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if ((instr->opcode == aco_opcode::s_mov_b32 || instr->opcode == aco_opcode::s_mov_b64 || instr->opcode == aco_opcode::v_mov_b32) &&
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!instr->definitions[0].isFixed() && instr->operands[0].isTemp() && instr->operands[0].regClass() == instr->definitions[0].regClass() &&
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!instr->isDPP() && !((int)instr->format & (int)Format::SDWA)) {
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ctx.renames[instr->definitions[0].tempId()] = instr->operands[0].getTemp();
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}
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if (instr->opcode == aco_opcode::p_discard_if ||
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instr->opcode == aco_opcode::p_demote_to_helper)
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ctx.exec_id++;
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instr->pass_flags = ctx.exec_id;
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std::pair<expr_set::iterator, bool> res = ctx.expr_values.emplace(instr.get(), block.index);
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/* if there was already an expression with the same value number */
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if (!res.second) {
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Instruction* orig_instr = res.first->first;
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assert(instr->definitions.size() == orig_instr->definitions.size());
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/* check if the original instruction dominates the current one */
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if (dominates(ctx, res.first->second, block.index) &&
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ctx.program->blocks[res.first->second].fp_mode.canReplace(block.fp_mode)) {
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for (unsigned i = 0; i < instr->definitions.size(); i++) {
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assert(instr->definitions[i].regClass() == orig_instr->definitions[i].regClass());
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ctx.renames[instr->definitions[i].tempId()] = orig_instr->definitions[i].getTemp();
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}
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} else {
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ctx.expr_values.erase(res.first);
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ctx.expr_values.emplace(instr.get(), block.index);
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new_instructions.emplace_back(std::move(instr));
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}
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} else {
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new_instructions.emplace_back(std::move(instr));
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}
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}
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block.instructions = std::move(new_instructions);
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}
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void rename_phi_operands(Block& block, std::map<uint32_t, Temp>& renames)
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{
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for (aco_ptr<Instruction>& phi : block.instructions) {
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if (phi->opcode != aco_opcode::p_phi && phi->opcode != aco_opcode::p_linear_phi)
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break;
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for (Operand& op : phi->operands) {
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if (!op.isTemp())
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continue;
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auto it = renames.find(op.tempId());
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if (it != renames.end())
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op.setTemp(it->second);
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}
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}
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}
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} /* end namespace */
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void value_numbering(Program* program)
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{
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vn_ctx ctx(program);
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std::vector<unsigned> loop_headers;
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for (Block& block : program->blocks) {
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assert(ctx.exec_id > 0);
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/* decrement exec_id when leaving nested control flow */
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if (block.kind & block_kind_loop_header)
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loop_headers.push_back(block.index);
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if (block.kind & block_kind_merge) {
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ctx.exec_id--;
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} else if (block.kind & block_kind_loop_exit) {
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ctx.exec_id -= program->blocks[loop_headers.back()].logical_preds.size();
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ctx.exec_id -= block.logical_preds.size();
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loop_headers.pop_back();
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}
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if (block.logical_idom != -1)
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process_block(ctx, block);
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else
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rename_phi_operands(block, ctx.renames);
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/* increment exec_id when entering nested control flow */
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if (block.kind & block_kind_branch ||
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block.kind & block_kind_loop_preheader ||
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block.kind & block_kind_break ||
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block.kind & block_kind_continue)
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ctx.exec_id++;
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else if (block.kind & block_kind_continue_or_break)
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ctx.exec_id += 2;
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}
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/* rename loop header phi operands */
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for (Block& block : program->blocks) {
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if (block.kind & block_kind_loop_header)
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rename_phi_operands(block, ctx.renames);
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}
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}
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}
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