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de7ed0ba55
Coffee Lake has a gen9 graphics following KBL. From 3D perspective, CFL is a clone of KBL/SKL features. v2: Change commit message, correct alignment <Anuj Phogat> v3: Update IDs. v4: Initialize l3_banks, correct nomenclature <Anuj> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Benjamin Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
733 lines
22 KiB
C
733 lines
22 KiB
C
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include "gen_device_info.h"
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#include "compiler/shader_enums.h"
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static const struct gen_device_info gen_device_info_i965 = {
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.gen = 4,
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.has_negative_rhw_bug = true,
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.num_slices = 1,
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.num_thread_per_eu = 4,
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.max_vs_threads = 16,
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.max_gs_threads = 2,
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.max_wm_threads = 8 * 4,
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.urb = {
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.size = 256,
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},
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.timestamp_frequency = 12500000,
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};
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static const struct gen_device_info gen_device_info_g4x = {
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.gen = 4,
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.has_pln = true,
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.has_compr4 = true,
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.has_surface_tile_offset = true,
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.is_g4x = true,
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.num_slices = 1,
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.num_thread_per_eu = 5,
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.max_vs_threads = 32,
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.max_gs_threads = 2,
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.max_wm_threads = 10 * 5,
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.urb = {
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.size = 384,
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},
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.timestamp_frequency = 12500000,
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};
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static const struct gen_device_info gen_device_info_ilk = {
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.gen = 5,
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.has_pln = true,
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.has_compr4 = true,
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.has_surface_tile_offset = true,
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.num_slices = 1,
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.num_thread_per_eu = 6,
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.max_vs_threads = 72,
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.max_gs_threads = 32,
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.max_wm_threads = 12 * 6,
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.urb = {
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.size = 1024,
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},
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.timestamp_frequency = 12500000,
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};
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static const struct gen_device_info gen_device_info_snb_gt1 = {
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.gen = 6,
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.gt = 1,
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.has_hiz_and_separate_stencil = true,
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.has_llc = true,
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.has_pln = true,
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.has_surface_tile_offset = true,
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.needs_unlit_centroid_workaround = true,
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.num_slices = 1,
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.num_thread_per_eu = 6, /* Not confirmed */
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.max_vs_threads = 24,
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.max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
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.max_wm_threads = 40,
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.urb = {
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.size = 32,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 24,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 256,
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[MESA_SHADER_GEOMETRY] = 256,
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},
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},
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.timestamp_frequency = 12500000,
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};
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static const struct gen_device_info gen_device_info_snb_gt2 = {
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.gen = 6,
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.gt = 2,
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.has_hiz_and_separate_stencil = true,
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.has_llc = true,
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.has_pln = true,
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.has_surface_tile_offset = true,
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.needs_unlit_centroid_workaround = true,
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.num_slices = 1,
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.num_thread_per_eu = 6, /* Not confirmed */
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.max_vs_threads = 60,
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.max_gs_threads = 60,
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.max_wm_threads = 80,
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.urb = {
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.size = 64,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 24,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 256,
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[MESA_SHADER_GEOMETRY] = 256,
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},
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},
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.timestamp_frequency = 12500000,
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};
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#define GEN7_FEATURES \
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.gen = 7, \
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.has_hiz_and_separate_stencil = true, \
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.must_use_separate_stencil = true, \
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.has_llc = true, \
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.has_pln = true, \
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.has_surface_tile_offset = true, \
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.timestamp_frequency = 12500000
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static const struct gen_device_info gen_device_info_ivb_gt1 = {
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GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
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.num_slices = 1,
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.num_thread_per_eu = 6,
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.l3_banks = 2,
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.max_vs_threads = 36,
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.max_tcs_threads = 36,
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.max_tes_threads = 36,
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.max_gs_threads = 36,
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.max_wm_threads = 48,
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.max_cs_threads = 36,
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.urb = {
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.size = 128,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 32,
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[MESA_SHADER_TESS_EVAL] = 10,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 512,
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[MESA_SHADER_TESS_CTRL] = 32,
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[MESA_SHADER_TESS_EVAL] = 288,
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[MESA_SHADER_GEOMETRY] = 192,
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},
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},
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};
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static const struct gen_device_info gen_device_info_ivb_gt2 = {
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GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
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.num_slices = 1,
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.num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
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* @max_wm_threads ... */
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.l3_banks = 4,
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.max_vs_threads = 128,
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.max_tcs_threads = 128,
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.max_tes_threads = 128,
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.max_gs_threads = 128,
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.max_wm_threads = 172,
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.max_cs_threads = 64,
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.urb = {
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.size = 256,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 32,
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[MESA_SHADER_TESS_EVAL] = 10,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 704,
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[MESA_SHADER_TESS_CTRL] = 64,
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[MESA_SHADER_TESS_EVAL] = 448,
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[MESA_SHADER_GEOMETRY] = 320,
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},
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},
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};
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static const struct gen_device_info gen_device_info_byt = {
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GEN7_FEATURES, .is_baytrail = true, .gt = 1,
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.num_slices = 1,
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.num_thread_per_eu = 8,
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.l3_banks = 1,
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.has_llc = false,
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.max_vs_threads = 36,
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.max_tcs_threads = 36,
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.max_tes_threads = 36,
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.max_gs_threads = 36,
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.max_wm_threads = 48,
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.max_cs_threads = 32,
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.urb = {
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.size = 128,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 32,
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[MESA_SHADER_TESS_EVAL] = 10,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 512,
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[MESA_SHADER_TESS_CTRL] = 32,
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[MESA_SHADER_TESS_EVAL] = 288,
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[MESA_SHADER_GEOMETRY] = 192,
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},
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},
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};
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#define HSW_FEATURES \
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GEN7_FEATURES, \
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.is_haswell = true, \
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.supports_simd16_3src = true, \
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.has_resource_streamer = true
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static const struct gen_device_info gen_device_info_hsw_gt1 = {
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HSW_FEATURES, .gt = 1,
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.num_slices = 1,
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.num_thread_per_eu = 7,
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.l3_banks = 2,
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.max_vs_threads = 70,
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.max_tcs_threads = 70,
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.max_tes_threads = 70,
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.max_gs_threads = 70,
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.max_wm_threads = 102,
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.max_cs_threads = 70,
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.urb = {
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.size = 128,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 32,
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[MESA_SHADER_TESS_EVAL] = 10,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 640,
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[MESA_SHADER_TESS_CTRL] = 64,
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[MESA_SHADER_TESS_EVAL] = 384,
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[MESA_SHADER_GEOMETRY] = 256,
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},
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},
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};
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static const struct gen_device_info gen_device_info_hsw_gt2 = {
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HSW_FEATURES, .gt = 2,
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.num_slices = 1,
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.num_thread_per_eu = 7,
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.l3_banks = 4,
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.max_vs_threads = 280,
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.max_tcs_threads = 256,
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.max_tes_threads = 280,
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.max_gs_threads = 256,
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.max_wm_threads = 204,
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.max_cs_threads = 70,
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.urb = {
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.size = 256,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 64,
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[MESA_SHADER_TESS_EVAL] = 10,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 1664,
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[MESA_SHADER_TESS_CTRL] = 128,
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[MESA_SHADER_TESS_EVAL] = 960,
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[MESA_SHADER_GEOMETRY] = 640,
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},
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},
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};
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static const struct gen_device_info gen_device_info_hsw_gt3 = {
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HSW_FEATURES, .gt = 3,
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.num_slices = 2,
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.num_thread_per_eu = 7,
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.l3_banks = 8,
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.max_vs_threads = 280,
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.max_tcs_threads = 256,
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.max_tes_threads = 280,
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.max_gs_threads = 256,
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.max_wm_threads = 408,
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.max_cs_threads = 70,
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.urb = {
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.size = 512,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 64,
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[MESA_SHADER_TESS_EVAL] = 10,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 1664,
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[MESA_SHADER_TESS_CTRL] = 128,
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[MESA_SHADER_TESS_EVAL] = 960,
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[MESA_SHADER_GEOMETRY] = 640,
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},
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},
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};
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#define GEN8_FEATURES \
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.gen = 8, \
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.has_hiz_and_separate_stencil = true, \
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.has_resource_streamer = true, \
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.must_use_separate_stencil = true, \
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.has_llc = true, \
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.has_pln = true, \
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.supports_simd16_3src = true, \
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.has_surface_tile_offset = true, \
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.max_vs_threads = 504, \
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.max_tcs_threads = 504, \
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.max_tes_threads = 504, \
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.max_gs_threads = 504, \
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.max_wm_threads = 384, \
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.timestamp_frequency = 12500000
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static const struct gen_device_info gen_device_info_bdw_gt1 = {
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GEN8_FEATURES, .gt = 1,
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.is_broadwell = true,
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.num_slices = 1,
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.num_thread_per_eu = 7,
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.l3_banks = 2,
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.max_cs_threads = 42,
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.urb = {
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.size = 192,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 64,
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[MESA_SHADER_TESS_EVAL] = 34,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 2560,
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[MESA_SHADER_TESS_CTRL] = 504,
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[MESA_SHADER_TESS_EVAL] = 1536,
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[MESA_SHADER_GEOMETRY] = 960,
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},
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}
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};
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static const struct gen_device_info gen_device_info_bdw_gt2 = {
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GEN8_FEATURES, .gt = 2,
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.is_broadwell = true,
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.num_slices = 1,
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.num_thread_per_eu = 7,
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.l3_banks = 4,
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.max_cs_threads = 56,
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.urb = {
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.size = 384,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 64,
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[MESA_SHADER_TESS_EVAL] = 34,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 2560,
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[MESA_SHADER_TESS_CTRL] = 504,
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[MESA_SHADER_TESS_EVAL] = 1536,
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[MESA_SHADER_GEOMETRY] = 960,
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},
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}
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};
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static const struct gen_device_info gen_device_info_bdw_gt3 = {
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GEN8_FEATURES, .gt = 3,
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.is_broadwell = true,
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.num_slices = 2,
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.num_thread_per_eu = 7,
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.l3_banks = 8,
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.max_cs_threads = 56,
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.urb = {
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.size = 384,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 64,
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[MESA_SHADER_TESS_EVAL] = 34,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 2560,
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[MESA_SHADER_TESS_CTRL] = 504,
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[MESA_SHADER_TESS_EVAL] = 1536,
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[MESA_SHADER_GEOMETRY] = 960,
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},
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}
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};
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static const struct gen_device_info gen_device_info_chv = {
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GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
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.has_llc = false,
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.num_slices = 1,
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.num_thread_per_eu = 7,
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.l3_banks = 2,
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.max_vs_threads = 80,
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.max_tcs_threads = 80,
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.max_tes_threads = 80,
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.max_gs_threads = 80,
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.max_wm_threads = 128,
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.max_cs_threads = 6 * 7,
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.urb = {
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.size = 192,
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.min_entries = {
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[MESA_SHADER_VERTEX] = 34,
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[MESA_SHADER_TESS_EVAL] = 34,
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},
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.max_entries = {
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[MESA_SHADER_VERTEX] = 640,
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[MESA_SHADER_TESS_CTRL] = 80,
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[MESA_SHADER_TESS_EVAL] = 384,
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[MESA_SHADER_GEOMETRY] = 256,
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},
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}
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};
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#define GEN9_HW_INFO \
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.gen = 9, \
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.max_vs_threads = 336, \
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.max_gs_threads = 336, \
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.max_tcs_threads = 336, \
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.max_tes_threads = 336, \
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.max_cs_threads = 56, \
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.timestamp_frequency = 12000000, \
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.urb = { \
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.size = 384, \
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.min_entries = { \
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[MESA_SHADER_VERTEX] = 64, \
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[MESA_SHADER_TESS_EVAL] = 34, \
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}, \
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.max_entries = { \
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[MESA_SHADER_VERTEX] = 1856, \
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[MESA_SHADER_TESS_CTRL] = 672, \
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[MESA_SHADER_TESS_EVAL] = 1120, \
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[MESA_SHADER_GEOMETRY] = 640, \
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}, \
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}
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#define GEN9_LP_FEATURES \
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GEN8_FEATURES, \
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GEN9_HW_INFO, \
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.gt = 1, \
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.has_llc = false, \
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.num_slices = 1, \
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.num_thread_per_eu = 6, \
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.max_vs_threads = 112, \
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.max_tcs_threads = 112, \
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.max_tes_threads = 112, \
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.max_gs_threads = 112, \
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.max_cs_threads = 6 * 6, \
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.timestamp_frequency = 19200000, \
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.urb = { \
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.size = 192, \
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.min_entries = { \
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[MESA_SHADER_VERTEX] = 34, \
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[MESA_SHADER_TESS_EVAL] = 34, \
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}, \
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.max_entries = { \
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[MESA_SHADER_VERTEX] = 704, \
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[MESA_SHADER_TESS_CTRL] = 256, \
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[MESA_SHADER_TESS_EVAL] = 416, \
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[MESA_SHADER_GEOMETRY] = 256, \
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}, \
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}
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#define GEN9_LP_FEATURES_2X6 \
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GEN9_LP_FEATURES, \
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.max_vs_threads = 56, \
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.max_tcs_threads = 56, \
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.max_tes_threads = 56, \
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.max_gs_threads = 56, \
|
|
.max_cs_threads = 6 * 6, \
|
|
.urb = { \
|
|
.size = 128, \
|
|
.min_entries = { \
|
|
[MESA_SHADER_VERTEX] = 34, \
|
|
[MESA_SHADER_TESS_EVAL] = 34, \
|
|
}, \
|
|
.max_entries = { \
|
|
[MESA_SHADER_VERTEX] = 352, \
|
|
[MESA_SHADER_TESS_CTRL] = 128, \
|
|
[MESA_SHADER_TESS_EVAL] = 208, \
|
|
[MESA_SHADER_GEOMETRY] = 128, \
|
|
}, \
|
|
}
|
|
|
|
#define GEN9_FEATURES \
|
|
GEN8_FEATURES, \
|
|
GEN9_HW_INFO, \
|
|
.num_thread_per_eu = 7
|
|
|
|
static const struct gen_device_info gen_device_info_skl_gt1 = {
|
|
GEN9_FEATURES, .gt = 1,
|
|
.is_skylake = true,
|
|
.num_slices = 1,
|
|
.l3_banks = 2,
|
|
.urb.size = 192,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_skl_gt2 = {
|
|
GEN9_FEATURES, .gt = 2,
|
|
.is_skylake = true,
|
|
.num_slices = 1,
|
|
.l3_banks = 4,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_skl_gt3 = {
|
|
GEN9_FEATURES, .gt = 3,
|
|
.is_skylake = true,
|
|
.num_slices = 2,
|
|
.l3_banks = 8,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_skl_gt4 = {
|
|
GEN9_FEATURES, .gt = 4,
|
|
.is_skylake = true,
|
|
.num_slices = 3,
|
|
.l3_banks = 12,
|
|
/* From the "L3 Allocation and Programming" documentation:
|
|
*
|
|
* "URB is limited to 1008KB due to programming restrictions. This is not a
|
|
* restriction of the L3 implementation, but of the FF and other clients.
|
|
* Therefore, in a GT4 implementation it is possible for the programmed
|
|
* allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
|
|
* only 1008KB of this will be used."
|
|
*/
|
|
.urb.size = 1008 / 3,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_bxt = {
|
|
GEN9_LP_FEATURES,
|
|
.is_broxton = true,
|
|
.l3_banks = 2,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_bxt_2x6 = {
|
|
GEN9_LP_FEATURES_2X6,
|
|
.is_broxton = true,
|
|
.l3_banks = 1,
|
|
};
|
|
/*
|
|
* Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
|
|
* There's no KBL entry. Using the default SKL (GEN9) GS entries value.
|
|
*/
|
|
|
|
static const struct gen_device_info gen_device_info_kbl_gt1 = {
|
|
GEN9_FEATURES,
|
|
.is_kabylake = true,
|
|
.gt = 1,
|
|
|
|
.max_cs_threads = 7 * 6,
|
|
.urb.size = 192,
|
|
.num_slices = 1,
|
|
.l3_banks = 2,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
|
|
GEN9_FEATURES,
|
|
.is_kabylake = true,
|
|
.gt = 1,
|
|
|
|
.max_cs_threads = 7 * 6,
|
|
.num_slices = 1,
|
|
.l3_banks = 4,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_kbl_gt2 = {
|
|
GEN9_FEATURES,
|
|
.is_kabylake = true,
|
|
.gt = 2,
|
|
|
|
.num_slices = 1,
|
|
.l3_banks = 4,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_kbl_gt3 = {
|
|
GEN9_FEATURES,
|
|
.is_kabylake = true,
|
|
.gt = 3,
|
|
|
|
.num_slices = 2,
|
|
.l3_banks = 8,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_kbl_gt4 = {
|
|
GEN9_FEATURES,
|
|
.is_kabylake = true,
|
|
.gt = 4,
|
|
|
|
/*
|
|
* From the "L3 Allocation and Programming" documentation:
|
|
*
|
|
* "URB is limited to 1008KB due to programming restrictions. This
|
|
* is not a restriction of the L3 implementation, but of the FF and
|
|
* other clients. Therefore, in a GT4 implementation it is
|
|
* possible for the programmed allocation of the L3 data array to
|
|
* provide 3*384KB=1152KB for URB, but only 1008KB of this
|
|
* will be used."
|
|
*/
|
|
.urb.size = 1008 / 3,
|
|
.num_slices = 3,
|
|
.l3_banks = 12,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_glk = {
|
|
GEN9_LP_FEATURES,
|
|
.is_geminilake = true,
|
|
.l3_banks = 2,
|
|
};
|
|
|
|
/*TODO: Initialize l3_banks when we know the number. */
|
|
static const struct gen_device_info gen_device_info_glk_2x6 = {
|
|
GEN9_LP_FEATURES_2X6,
|
|
.is_geminilake = true,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_cfl_gt1 = {
|
|
GEN9_FEATURES,
|
|
.is_coffeelake = true,
|
|
.gt = 1,
|
|
|
|
.num_slices = 1,
|
|
.l3_banks = 2,
|
|
};
|
|
static const struct gen_device_info gen_device_info_cfl_gt2 = {
|
|
GEN9_FEATURES,
|
|
.is_coffeelake = true,
|
|
.gt = 2,
|
|
|
|
.num_slices = 1,
|
|
.l3_banks = 4,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_cfl_gt3 = {
|
|
GEN9_FEATURES,
|
|
.is_coffeelake = true,
|
|
.gt = 3,
|
|
|
|
.num_slices = 2,
|
|
.l3_banks = 8,
|
|
};
|
|
|
|
#define GEN10_HW_INFO \
|
|
.gen = 10, \
|
|
.num_thread_per_eu = 7, \
|
|
.max_vs_threads = 728, \
|
|
.max_gs_threads = 432, \
|
|
.max_tcs_threads = 432, \
|
|
.max_tes_threads = 624, \
|
|
.max_cs_threads = 56, \
|
|
.timestamp_frequency = 19200000, \
|
|
.urb = { \
|
|
.size = 256, \
|
|
.min_entries = { \
|
|
[MESA_SHADER_VERTEX] = 64, \
|
|
[MESA_SHADER_TESS_EVAL] = 34, \
|
|
}, \
|
|
.max_entries = { \
|
|
[MESA_SHADER_VERTEX] = 3936, \
|
|
[MESA_SHADER_TESS_CTRL] = 896, \
|
|
[MESA_SHADER_TESS_EVAL] = 2064, \
|
|
[MESA_SHADER_GEOMETRY] = 832, \
|
|
}, \
|
|
}
|
|
|
|
#define GEN10_FEATURES(_gt, _slices, _l3) \
|
|
GEN8_FEATURES, \
|
|
GEN10_HW_INFO, \
|
|
.gt = _gt, .num_slices = _slices, .l3_banks = _l3
|
|
|
|
static const struct gen_device_info gen_device_info_cnl_2x8 = {
|
|
/* GT0.5 */
|
|
GEN10_FEATURES(1, 1, 2),
|
|
.is_cannonlake = true,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_cnl_3x8 = {
|
|
/* GT1 */
|
|
GEN10_FEATURES(1, 1, 3),
|
|
.is_cannonlake = true,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_cnl_4x8 = {
|
|
/* GT 1.5 */
|
|
GEN10_FEATURES(1, 2, 6),
|
|
.is_cannonlake = true,
|
|
};
|
|
|
|
static const struct gen_device_info gen_device_info_cnl_5x8 = {
|
|
/* GT2 */
|
|
GEN10_FEATURES(2, 2, 6),
|
|
.is_cannonlake = true,
|
|
};
|
|
|
|
bool
|
|
gen_get_device_info(int devid, struct gen_device_info *devinfo)
|
|
{
|
|
switch (devid) {
|
|
#undef CHIPSET
|
|
#define CHIPSET(id, family, name) \
|
|
case id: *devinfo = gen_device_info_##family; break;
|
|
#include "pci_ids/i965_pci_ids.h"
|
|
default:
|
|
fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
|
|
return false;
|
|
}
|
|
|
|
/* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
|
|
*
|
|
* "Scratch Space per slice is computed based on 4 sub-slices. SW must
|
|
* allocate scratch space enough so that each slice has 4 slices allowed."
|
|
*
|
|
* The equivalent internal documentation says that this programming note
|
|
* applies to all Gen9+ platforms.
|
|
*
|
|
* The hardware typically calculates the scratch space pointer by taking
|
|
* the base address, and adding per-thread-scratch-space * thread ID.
|
|
* Extra padding can be necessary depending how the thread IDs are
|
|
* calculated for a particular shader stage.
|
|
*/
|
|
if (devinfo->gen >= 9) {
|
|
devinfo->max_wm_threads = 64 /* threads-per-PSD */
|
|
* devinfo->num_slices
|
|
* 4; /* effective subslices per slice */
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
const char *
|
|
gen_get_device_name(int devid)
|
|
{
|
|
switch (devid) {
|
|
#undef CHIPSET
|
|
#define CHIPSET(id, family, name) case id: return name;
|
|
#include "pci_ids/i965_pci_ids.h"
|
|
default:
|
|
return NULL;
|
|
}
|
|
}
|