mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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de54b4b18f
Previously, we were including gen7_pack.h, gen75_pack.h, and gen8_pack.h in anv_private.h. As we add more gens, this is going to become untenable. This commit moves things around so that we only use the pack headers when and if we need them.
935 lines
38 KiB
C
935 lines
38 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "gen7_pack.h"
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static void
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gen7_cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
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{
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static const uint32_t push_constant_opcodes[] = {
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[VK_SHADER_STAGE_VERTEX] = 21,
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[VK_SHADER_STAGE_TESS_CONTROL] = 25, /* HS */
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[VK_SHADER_STAGE_TESS_EVALUATION] = 26, /* DS */
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[VK_SHADER_STAGE_GEOMETRY] = 22,
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[VK_SHADER_STAGE_FRAGMENT] = 23,
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[VK_SHADER_STAGE_COMPUTE] = 0,
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};
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VkShaderStage stage;
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VkShaderStageFlags flushed = 0;
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for_each_bit(stage, cmd_buffer->state.push_constants_dirty) {
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struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
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if (state.offset == 0)
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continue;
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CONSTANT_VS,
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._3DCommandSubOpcode = push_constant_opcodes[stage],
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.ConstantBody = {
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.PointerToConstantBuffer0 = { .offset = state.offset },
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.ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
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});
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flushed |= 1 << stage;
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}
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cmd_buffer->state.push_constants_dirty &= ~flushed;
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}
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void
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gen7_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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struct anv_bo *scratch_bo = NULL;
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cmd_buffer->state.scratch_size =
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anv_block_pool_size(&device->scratch_block_pool);
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if (cmd_buffer->state.scratch_size > 0)
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scratch_bo = &device->scratch_block_pool.bo;
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anv_batch_emit(&cmd_buffer->batch, GEN7_STATE_BASE_ADDRESS,
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.GeneralStateBaseAddress = { scratch_bo, 0 },
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.GeneralStateMemoryObjectControlState = GEN7_MOCS,
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.GeneralStateBaseAddressModifyEnable = true,
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.GeneralStateAccessUpperBound = { scratch_bo, scratch_bo->size },
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.GeneralStateAccessUpperBoundModifyEnable = true,
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.SurfaceStateBaseAddress = anv_cmd_buffer_surface_base_address(cmd_buffer),
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.SurfaceStateMemoryObjectControlState = GEN7_MOCS,
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.SurfaceStateBaseAddressModifyEnable = true,
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.DynamicStateBaseAddress = { &device->dynamic_state_block_pool.bo, 0 },
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.DynamicStateMemoryObjectControlState = GEN7_MOCS,
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.DynamicStateBaseAddressModifyEnable = true,
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.DynamicStateAccessUpperBound = { &device->dynamic_state_block_pool.bo,
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device->dynamic_state_block_pool.bo.size },
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.DynamicStateAccessUpperBoundModifyEnable = true,
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.IndirectObjectBaseAddress = { NULL, 0 },
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.IndirectObjectMemoryObjectControlState = GEN7_MOCS,
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.IndirectObjectBaseAddressModifyEnable = true,
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.IndirectObjectAccessUpperBound = { NULL, 0xffffffff },
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.IndirectObjectAccessUpperBoundModifyEnable = true,
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.InstructionBaseAddress = { &device->instruction_block_pool.bo, 0 },
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.InstructionMemoryObjectControlState = GEN7_MOCS,
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.InstructionBaseAddressModifyEnable = true,
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.InstructionAccessUpperBound = { &device->instruction_block_pool.bo,
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device->instruction_block_pool.bo.size },
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.InstructionAccessUpperBoundModifyEnable = true);
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/* After re-setting the surface state base address, we have to do some
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* cache flusing so that the sampler engine will pick up the new
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* SURFACE_STATE objects and binding tables. From the Broadwell PRM,
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* Shared Function > 3D Sampler > State > State Caching (page 96):
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*
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* Coherency with system memory in the state cache, like the texture
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* cache is handled partially by software. It is expected that the
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* command stream or shader will issue Cache Flush operation or
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* Cache_Flush sampler message to ensure that the L1 cache remains
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* coherent with system memory.
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*
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* [...]
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*
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* Whenever the value of the Dynamic_State_Base_Addr,
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* Surface_State_Base_Addr are altered, the L1 state cache must be
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* invalidated to ensure the new surface or sampler state is fetched
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* from system memory.
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*
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* The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
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* which, according the PIPE_CONTROL instruction documentation in the
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* Broadwell PRM:
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*
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* Setting this bit is independent of any other bit in this packet.
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* This bit controls the invalidation of the L1 and L2 state caches
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* at the top of the pipe i.e. at the parsing time.
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*
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* Unfortunately, experimentation seems to indicate that state cache
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* invalidation through a PIPE_CONTROL does nothing whatsoever in
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* regards to surface state and binding tables. In stead, it seems that
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* invalidating the texture cache is what is actually needed.
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*
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* XXX: As far as we have been able to determine through
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* experimentation, shows that flush the texture cache appears to be
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* sufficient. The theory here is that all of the sampling/rendering
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* units cache the binding table in the texture cache. However, we have
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* yet to be able to actually confirm this.
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*/
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anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
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.TextureCacheInvalidationEnable = true);
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}
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static VkResult
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flush_descriptor_set(struct anv_cmd_buffer *cmd_buffer, VkShaderStage stage)
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{
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struct anv_state surfaces = { 0, }, samplers = { 0, };
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VkResult result;
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result = anv_cmd_buffer_emit_samplers(cmd_buffer, stage, &samplers);
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if (result != VK_SUCCESS)
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return result;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer, stage, &surfaces);
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if (result != VK_SUCCESS)
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return result;
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static const uint32_t sampler_state_opcodes[] = {
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[VK_SHADER_STAGE_VERTEX] = 43,
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[VK_SHADER_STAGE_TESS_CONTROL] = 44, /* HS */
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[VK_SHADER_STAGE_TESS_EVALUATION] = 45, /* DS */
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[VK_SHADER_STAGE_GEOMETRY] = 46,
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[VK_SHADER_STAGE_FRAGMENT] = 47,
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[VK_SHADER_STAGE_COMPUTE] = 0,
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};
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static const uint32_t binding_table_opcodes[] = {
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[VK_SHADER_STAGE_VERTEX] = 38,
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[VK_SHADER_STAGE_TESS_CONTROL] = 39,
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[VK_SHADER_STAGE_TESS_EVALUATION] = 40,
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[VK_SHADER_STAGE_GEOMETRY] = 41,
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[VK_SHADER_STAGE_FRAGMENT] = 42,
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[VK_SHADER_STAGE_COMPUTE] = 0,
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};
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if (samplers.alloc_size > 0) {
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anv_batch_emit(&cmd_buffer->batch,
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GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS,
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._3DCommandSubOpcode = sampler_state_opcodes[stage],
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.PointertoVSSamplerState = samplers.offset);
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}
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if (surfaces.alloc_size > 0) {
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anv_batch_emit(&cmd_buffer->batch,
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GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS,
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._3DCommandSubOpcode = binding_table_opcodes[stage],
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.PointertoVSBindingTable = surfaces.offset);
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}
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return VK_SUCCESS;
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}
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void
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gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
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{
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VkShaderStage s;
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VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
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cmd_buffer->state.pipeline->active_stages;
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VkResult result = VK_SUCCESS;
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for_each_bit(s, dirty) {
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result = flush_descriptor_set(cmd_buffer, s);
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if (result != VK_SUCCESS)
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break;
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}
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if (result != VK_SUCCESS) {
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assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
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result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
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assert(result == VK_SUCCESS);
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/* Re-emit state base addresses so we get the new surface state base
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* address before we start emitting binding tables etc.
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*/
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anv_cmd_buffer_emit_state_base_address(cmd_buffer);
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/* Re-emit all active binding tables */
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for_each_bit(s, cmd_buffer->state.pipeline->active_stages) {
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result = flush_descriptor_set(cmd_buffer, s);
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/* It had better succeed this time */
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assert(result == VK_SUCCESS);
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}
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}
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cmd_buffer->state.descriptors_dirty &= ~cmd_buffer->state.pipeline->active_stages;
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}
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static inline int64_t
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clamp_int64(int64_t x, int64_t min, int64_t max)
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{
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if (x < min)
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return min;
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else if (x < max)
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return x;
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else
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return max;
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}
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static void
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emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
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uint32_t count, const VkRect2D *scissors)
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{
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struct anv_state scissor_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 32, 32);
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for (uint32_t i = 0; i < count; i++) {
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const VkRect2D *s = &scissors[i];
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/* Since xmax and ymax are inclusive, we have to have xmax < xmin or
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* ymax < ymin for empty clips. In case clip x, y, width height are all
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* 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
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* what we want. Just special case empty clips and produce a canonical
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* empty clip. */
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static const struct GEN7_SCISSOR_RECT empty_scissor = {
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.ScissorRectangleYMin = 1,
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.ScissorRectangleXMin = 1,
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.ScissorRectangleYMax = 0,
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.ScissorRectangleXMax = 0
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};
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const int max = 0xffff;
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struct GEN7_SCISSOR_RECT scissor = {
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/* Do this math using int64_t so overflow gets clamped correctly. */
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.ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
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.ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
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.ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
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.ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
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};
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if (s->extent.width <= 0 || s->extent.height <= 0) {
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GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 32,
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&empty_scissor);
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} else {
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GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 32, &scissor);
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}
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}
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_SCISSOR_STATE_POINTERS,
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.ScissorRectPointer = scissor_state.offset);
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}
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void
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gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
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{
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if (cmd_buffer->state.dynamic.scissor.count > 0) {
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emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
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cmd_buffer->state.dynamic.scissor.scissors);
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} else {
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/* Emit a default scissor based on the currently bound framebuffer */
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emit_scissor_state(cmd_buffer, 1,
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&(VkRect2D) {
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.offset = { .x = 0, .y = 0, },
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.extent = {
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.width = cmd_buffer->state.framebuffer->width,
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.height = cmd_buffer->state.framebuffer->height,
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},
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});
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}
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}
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static const uint32_t vk_to_gen_index_type[] = {
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[VK_INDEX_TYPE_UINT16] = INDEX_WORD,
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[VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
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};
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void gen7_CmdBindIndexBuffer(
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VkCmdBuffer cmdBuffer,
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VkBuffer _buffer,
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VkDeviceSize offset,
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VkIndexType indexType)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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cmd_buffer->state.gen7.index_buffer = buffer;
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cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
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cmd_buffer->state.gen7.index_offset = offset;
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}
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static VkResult
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gen7_flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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struct anv_state surfaces = { 0, }, samplers = { 0, };
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VkResult result;
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result = anv_cmd_buffer_emit_samplers(cmd_buffer,
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VK_SHADER_STAGE_COMPUTE, &samplers);
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if (result != VK_SUCCESS)
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return result;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
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VK_SHADER_STAGE_COMPUTE, &surfaces);
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if (result != VK_SUCCESS)
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return result;
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struct GEN7_INTERFACE_DESCRIPTOR_DATA desc = {
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.KernelStartPointer = pipeline->cs_simd,
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.BindingTablePointer = surfaces.offset,
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.SamplerStatePointer = samplers.offset,
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.NumberofThreadsinGPGPUThreadGroup = 0 /* FIXME: Really? */
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};
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uint32_t size = GEN7_INTERFACE_DESCRIPTOR_DATA_length * sizeof(uint32_t);
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struct anv_state state =
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anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
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GEN7_INTERFACE_DESCRIPTOR_DATA_pack(NULL, state.map, &desc);
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anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
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.InterfaceDescriptorTotalLength = size,
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.InterfaceDescriptorDataStartAddress = state.offset);
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return VK_SUCCESS;
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}
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static void
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gen7_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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VkResult result;
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assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
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if (cmd_buffer->state.current_pipeline != GPGPU) {
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anv_batch_emit(&cmd_buffer->batch, GEN7_PIPELINE_SELECT,
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.PipelineSelection = GPGPU);
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cmd_buffer->state.current_pipeline = GPGPU;
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}
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if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
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(cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
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/* FIXME: figure out descriptors for gen7 */
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result = gen7_flush_compute_descriptor_set(cmd_buffer);
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assert(result == VK_SUCCESS);
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cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE;
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}
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cmd_buffer->state.compute_dirty = 0;
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}
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static void
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gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
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uint32_t *p;
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uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
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assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
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if (cmd_buffer->state.current_pipeline != _3D) {
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anv_batch_emit(&cmd_buffer->batch, GEN7_PIPELINE_SELECT,
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.PipelineSelection = _3D);
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cmd_buffer->state.current_pipeline = _3D;
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}
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if (vb_emit) {
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const uint32_t num_buffers = __builtin_popcount(vb_emit);
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const uint32_t num_dwords = 1 + num_buffers * 4;
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p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
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GEN7_3DSTATE_VERTEX_BUFFERS);
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uint32_t vb, i = 0;
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for_each_bit(vb, vb_emit) {
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struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
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uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
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struct GEN7_VERTEX_BUFFER_STATE state = {
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.VertexBufferIndex = vb,
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.BufferAccessType = pipeline->instancing_enable[vb] ? INSTANCEDATA : VERTEXDATA,
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.VertexBufferMemoryObjectControlState = GEN7_MOCS,
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.AddressModifyEnable = true,
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.BufferPitch = pipeline->binding_stride[vb],
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.BufferStartingAddress = { buffer->bo, buffer->offset + offset },
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.EndAddress = { buffer->bo, buffer->offset + buffer->size - 1},
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.InstanceDataStepRate = 1
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};
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GEN7_VERTEX_BUFFER_STATE_pack(&cmd_buffer->batch, &p[1 + i * 4], &state);
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i++;
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}
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}
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if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
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/* If somebody compiled a pipeline after starting a command buffer the
|
|
* scratch bo may have grown since we started this cmd buffer (and
|
|
* emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
|
|
* reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
|
|
if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
|
|
gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
|
|
|
|
anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
|
|
}
|
|
|
|
if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
|
|
cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
|
|
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
|
|
*
|
|
* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
|
|
* stall needs to be sent just prior to any 3DSTATE_VS,
|
|
* 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
|
|
* 3DSTATE_BINDING_TABLE_POINTER_VS,
|
|
* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
|
|
* PIPE_CONTROL needs to be sent before any combination of VS
|
|
* associated 3DSTATE."
|
|
*/
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
|
|
.DepthStallEnable = true,
|
|
.PostSyncOperation = WriteImmediateData,
|
|
.Address = { &cmd_buffer->device->workaround_bo, 0 });
|
|
}
|
|
|
|
if (cmd_buffer->state.descriptors_dirty)
|
|
gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
|
|
|
|
if (cmd_buffer->state.push_constants_dirty)
|
|
gen7_cmd_buffer_flush_push_constants(cmd_buffer);
|
|
|
|
/* We use the gen8 state here because it only contains the additional
|
|
* min/max fields and, since they occur at the end of the packet and
|
|
* don't change the stride, they work on gen7 too.
|
|
*/
|
|
if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
|
|
gen8_cmd_buffer_emit_viewport(cmd_buffer);
|
|
|
|
if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
|
|
gen7_cmd_buffer_emit_scissor(cmd_buffer);
|
|
|
|
if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
|
ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
|
|
ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
|
|
|
|
bool enable_bias = cmd_buffer->state.dynamic.depth_bias.bias != 0.0f ||
|
|
cmd_buffer->state.dynamic.depth_bias.slope_scaled != 0.0f;
|
|
|
|
uint32_t sf_dw[GEN7_3DSTATE_SF_length];
|
|
struct GEN7_3DSTATE_SF sf = {
|
|
GEN7_3DSTATE_SF_header,
|
|
.LineWidth = cmd_buffer->state.dynamic.line_width,
|
|
.GlobalDepthOffsetEnableSolid = enable_bias,
|
|
.GlobalDepthOffsetEnableWireframe = enable_bias,
|
|
.GlobalDepthOffsetEnablePoint = enable_bias,
|
|
.GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
|
|
.GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope_scaled,
|
|
.GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
|
|
};
|
|
GEN7_3DSTATE_SF_pack(NULL, sf_dw, &sf);
|
|
|
|
anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
|
|
}
|
|
|
|
if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
|
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
|
|
struct anv_state cc_state =
|
|
anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
|
|
GEN7_COLOR_CALC_STATE_length, 64);
|
|
struct GEN7_COLOR_CALC_STATE cc = {
|
|
.BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
|
|
.BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
|
|
.BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
|
|
.BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
|
|
.StencilReferenceValue =
|
|
cmd_buffer->state.dynamic.stencil_reference.front,
|
|
.BackFaceStencilReferenceValue =
|
|
cmd_buffer->state.dynamic.stencil_reference.back,
|
|
};
|
|
GEN7_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch,
|
|
GEN7_3DSTATE_CC_STATE_POINTERS,
|
|
.ColorCalcStatePointer = cc_state.offset);
|
|
}
|
|
|
|
if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
|
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
|
|
uint32_t depth_stencil_dw[GEN7_DEPTH_STENCIL_STATE_length];
|
|
|
|
struct GEN7_DEPTH_STENCIL_STATE depth_stencil = {
|
|
/* Is this what we need to do? */
|
|
.StencilBufferWriteEnable =
|
|
cmd_buffer->state.dynamic.stencil_write_mask.front != 0,
|
|
|
|
.StencilTestMask =
|
|
cmd_buffer->state.dynamic.stencil_compare_mask.front & 0xff,
|
|
.StencilWriteMask =
|
|
cmd_buffer->state.dynamic.stencil_write_mask.front & 0xff,
|
|
|
|
.BackfaceStencilTestMask =
|
|
cmd_buffer->state.dynamic.stencil_compare_mask.back & 0xff,
|
|
.BackfaceStencilWriteMask =
|
|
cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
|
|
};
|
|
GEN7_DEPTH_STENCIL_STATE_pack(NULL, depth_stencil_dw, &depth_stencil);
|
|
|
|
struct anv_state ds_state =
|
|
anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
|
|
pipeline->gen7.depth_stencil_state,
|
|
GEN7_DEPTH_STENCIL_STATE_length, 64);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch,
|
|
GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
|
|
.PointertoDEPTH_STENCIL_STATE = ds_state.offset);
|
|
}
|
|
|
|
if (cmd_buffer->state.gen7.index_buffer &&
|
|
cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
|
ANV_CMD_DIRTY_INDEX_BUFFER)) {
|
|
struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
|
|
uint32_t offset = cmd_buffer->state.gen7.index_offset;
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_INDEX_BUFFER,
|
|
.CutIndexEnable = pipeline->primitive_restart,
|
|
.IndexFormat = cmd_buffer->state.gen7.index_type,
|
|
.MemoryObjectControlState = GEN7_MOCS,
|
|
.BufferStartingAddress = { buffer->bo, buffer->offset + offset },
|
|
.BufferEndingAddress = { buffer->bo, buffer->offset + buffer->size });
|
|
}
|
|
|
|
cmd_buffer->state.vb_dirty &= ~vb_emit;
|
|
cmd_buffer->state.dirty = 0;
|
|
}
|
|
|
|
void gen7_CmdDraw(
|
|
VkCmdBuffer cmdBuffer,
|
|
uint32_t vertexCount,
|
|
uint32_t instanceCount,
|
|
uint32_t firstVertex,
|
|
uint32_t firstInstance)
|
|
{
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
|
|
|
gen7_cmd_buffer_flush_state(cmd_buffer);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
|
|
.VertexAccessType = SEQUENTIAL,
|
|
.PrimitiveTopologyType = pipeline->topology,
|
|
.VertexCountPerInstance = vertexCount,
|
|
.StartVertexLocation = firstVertex,
|
|
.InstanceCount = instanceCount,
|
|
.StartInstanceLocation = firstInstance,
|
|
.BaseVertexLocation = 0);
|
|
}
|
|
|
|
void gen7_CmdDrawIndexed(
|
|
VkCmdBuffer cmdBuffer,
|
|
uint32_t indexCount,
|
|
uint32_t instanceCount,
|
|
uint32_t firstIndex,
|
|
int32_t vertexOffset,
|
|
uint32_t firstInstance)
|
|
{
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
|
|
|
gen7_cmd_buffer_flush_state(cmd_buffer);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
|
|
.VertexAccessType = RANDOM,
|
|
.PrimitiveTopologyType = pipeline->topology,
|
|
.VertexCountPerInstance = indexCount,
|
|
.StartVertexLocation = firstIndex,
|
|
.InstanceCount = instanceCount,
|
|
.StartInstanceLocation = firstInstance,
|
|
.BaseVertexLocation = vertexOffset);
|
|
}
|
|
|
|
static void
|
|
gen7_batch_lrm(struct anv_batch *batch,
|
|
uint32_t reg, struct anv_bo *bo, uint32_t offset)
|
|
{
|
|
anv_batch_emit(batch, GEN7_MI_LOAD_REGISTER_MEM,
|
|
.RegisterAddress = reg,
|
|
.MemoryAddress = { bo, offset });
|
|
}
|
|
|
|
static void
|
|
gen7_batch_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
|
|
{
|
|
anv_batch_emit(batch, GEN7_MI_LOAD_REGISTER_IMM,
|
|
.RegisterOffset = reg,
|
|
.DataDWord = imm);
|
|
}
|
|
|
|
/* Auto-Draw / Indirect Registers */
|
|
#define GEN7_3DPRIM_END_OFFSET 0x2420
|
|
#define GEN7_3DPRIM_START_VERTEX 0x2430
|
|
#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
|
|
#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
|
|
#define GEN7_3DPRIM_START_INSTANCE 0x243C
|
|
#define GEN7_3DPRIM_BASE_VERTEX 0x2440
|
|
|
|
void gen7_CmdDrawIndirect(
|
|
VkCmdBuffer cmdBuffer,
|
|
VkBuffer _buffer,
|
|
VkDeviceSize offset,
|
|
uint32_t count,
|
|
uint32_t stride)
|
|
{
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
|
struct anv_bo *bo = buffer->bo;
|
|
uint32_t bo_offset = buffer->offset + offset;
|
|
|
|
gen7_cmd_buffer_flush_state(cmd_buffer);
|
|
|
|
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
|
|
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
|
|
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
|
|
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
|
|
gen7_batch_lri(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, 0);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
|
|
.IndirectParameterEnable = true,
|
|
.VertexAccessType = SEQUENTIAL,
|
|
.PrimitiveTopologyType = pipeline->topology);
|
|
}
|
|
|
|
void gen7_CmdDrawIndexedIndirect(
|
|
VkCmdBuffer cmdBuffer,
|
|
VkBuffer _buffer,
|
|
VkDeviceSize offset,
|
|
uint32_t count,
|
|
uint32_t stride)
|
|
{
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
|
struct anv_bo *bo = buffer->bo;
|
|
uint32_t bo_offset = buffer->offset + offset;
|
|
|
|
gen7_cmd_buffer_flush_state(cmd_buffer);
|
|
|
|
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
|
|
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
|
|
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
|
|
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
|
|
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
|
|
.IndirectParameterEnable = true,
|
|
.VertexAccessType = RANDOM,
|
|
.PrimitiveTopologyType = pipeline->topology);
|
|
}
|
|
|
|
void gen7_CmdDispatch(
|
|
VkCmdBuffer cmdBuffer,
|
|
uint32_t x,
|
|
uint32_t y,
|
|
uint32_t z)
|
|
{
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
|
|
struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
|
|
|
|
gen7_cmd_buffer_flush_compute_state(cmd_buffer);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_GPGPU_WALKER,
|
|
.SIMDSize = prog_data->simd_size / 16,
|
|
.ThreadDepthCounterMaximum = 0,
|
|
.ThreadHeightCounterMaximum = 0,
|
|
.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max,
|
|
.ThreadGroupIDXDimension = x,
|
|
.ThreadGroupIDYDimension = y,
|
|
.ThreadGroupIDZDimension = z,
|
|
.RightExecutionMask = pipeline->cs_right_mask,
|
|
.BottomExecutionMask = 0xffffffff);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_STATE_FLUSH);
|
|
}
|
|
|
|
#define GPGPU_DISPATCHDIMX 0x2500
|
|
#define GPGPU_DISPATCHDIMY 0x2504
|
|
#define GPGPU_DISPATCHDIMZ 0x2508
|
|
|
|
void gen7_CmdDispatchIndirect(
|
|
VkCmdBuffer cmdBuffer,
|
|
VkBuffer _buffer,
|
|
VkDeviceSize offset)
|
|
{
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
|
|
struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
|
|
struct anv_bo *bo = buffer->bo;
|
|
uint32_t bo_offset = buffer->offset + offset;
|
|
|
|
gen7_cmd_buffer_flush_compute_state(cmd_buffer);
|
|
|
|
gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
|
|
gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
|
|
gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMZ, bo, bo_offset + 8);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_GPGPU_WALKER,
|
|
.IndirectParameterEnable = true,
|
|
.SIMDSize = prog_data->simd_size / 16,
|
|
.ThreadDepthCounterMaximum = 0,
|
|
.ThreadHeightCounterMaximum = 0,
|
|
.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max,
|
|
.RightExecutionMask = pipeline->cs_right_mask,
|
|
.BottomExecutionMask = 0xffffffff);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_STATE_FLUSH);
|
|
}
|
|
|
|
void gen7_CmdPipelineBarrier(
|
|
VkCmdBuffer cmdBuffer,
|
|
VkPipelineStageFlags srcStageMask,
|
|
VkPipelineStageFlags destStageMask,
|
|
VkBool32 byRegion,
|
|
uint32_t memBarrierCount,
|
|
const void* const* ppMemBarriers)
|
|
{
|
|
stub();
|
|
}
|
|
|
|
static void
|
|
gen7_cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
|
|
{
|
|
const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
|
const struct anv_image_view *iview =
|
|
anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
|
|
const struct anv_image *image = iview ? iview->image : NULL;
|
|
const bool has_depth = iview && iview->format->depth_format;
|
|
const bool has_stencil = iview && iview->format->has_stencil;
|
|
|
|
/* Emit 3DSTATE_DEPTH_BUFFER */
|
|
if (has_depth) {
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_DEPTH_BUFFER,
|
|
.SurfaceType = SURFTYPE_2D,
|
|
.DepthWriteEnable = iview->format->depth_format,
|
|
.StencilWriteEnable = has_stencil,
|
|
.HierarchicalDepthBufferEnable = false,
|
|
.SurfaceFormat = iview->format->depth_format,
|
|
.SurfacePitch = image->depth_surface.stride - 1,
|
|
.SurfaceBaseAddress = {
|
|
.bo = image->bo,
|
|
.offset = image->depth_surface.offset,
|
|
},
|
|
.Height = fb->height - 1,
|
|
.Width = fb->width - 1,
|
|
.LOD = 0,
|
|
.Depth = 1 - 1,
|
|
.MinimumArrayElement = 0,
|
|
.DepthBufferObjectControlState = GEN7_MOCS,
|
|
.RenderTargetViewExtent = 1 - 1);
|
|
} else {
|
|
/* Even when no depth buffer is present, the hardware requires that
|
|
* 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
|
|
*
|
|
* If a null depth buffer is bound, the driver must instead bind depth as:
|
|
* 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
|
|
* 3DSTATE_DEPTH.Width = 1
|
|
* 3DSTATE_DEPTH.Height = 1
|
|
* 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
|
|
* 3DSTATE_DEPTH.SurfaceBaseAddress = 0
|
|
* 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
|
|
* 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
|
|
* 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
|
|
*
|
|
* The PRM is wrong, though. The width and height must be programmed to
|
|
* actual framebuffer's width and height, even when neither depth buffer
|
|
* nor stencil buffer is present.
|
|
*/
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_DEPTH_BUFFER,
|
|
.SurfaceType = SURFTYPE_2D,
|
|
.SurfaceFormat = D16_UNORM,
|
|
.Width = fb->width - 1,
|
|
.Height = fb->height - 1,
|
|
.StencilWriteEnable = has_stencil);
|
|
}
|
|
|
|
/* Emit 3DSTATE_STENCIL_BUFFER */
|
|
if (has_stencil) {
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_STENCIL_BUFFER,
|
|
.StencilBufferObjectControlState = GEN7_MOCS,
|
|
|
|
/* Stencil buffers have strange pitch. The PRM says:
|
|
*
|
|
* The pitch must be set to 2x the value computed based on width,
|
|
* as the stencil buffer is stored with two rows interleaved.
|
|
*/
|
|
.SurfacePitch = 2 * image->stencil_surface.stride - 1,
|
|
|
|
.SurfaceBaseAddress = {
|
|
.bo = image->bo,
|
|
.offset = image->offset + image->stencil_surface.offset,
|
|
});
|
|
} else {
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_STENCIL_BUFFER);
|
|
}
|
|
|
|
/* Disable hierarchial depth buffers. */
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_HIER_DEPTH_BUFFER);
|
|
|
|
/* Clear the clear params. */
|
|
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CLEAR_PARAMS);
|
|
}
|
|
|
|
void
|
|
gen7_cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
|
|
struct anv_subpass *subpass)
|
|
{
|
|
cmd_buffer->state.subpass = subpass;
|
|
cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
|
|
|
|
gen7_cmd_buffer_emit_depth_stencil(cmd_buffer);
|
|
}
|
|
|
|
static void
|
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begin_render_pass(struct anv_cmd_buffer *cmd_buffer,
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const VkRenderPassBeginInfo* pRenderPassBegin)
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{
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ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
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ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
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cmd_buffer->state.framebuffer = framebuffer;
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cmd_buffer->state.pass = pass;
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const VkRect2D *render_area = &pRenderPassBegin->renderArea;
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_DRAWING_RECTANGLE,
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.ClippedDrawingRectangleYMin = render_area->offset.y,
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.ClippedDrawingRectangleXMin = render_area->offset.x,
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.ClippedDrawingRectangleYMax =
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render_area->offset.y + render_area->extent.height - 1,
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.ClippedDrawingRectangleXMax =
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render_area->offset.x + render_area->extent.width - 1,
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.DrawingRectangleOriginY = 0,
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.DrawingRectangleOriginX = 0);
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anv_cmd_buffer_clear_attachments(cmd_buffer, pass,
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pRenderPassBegin->pClearValues);
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}
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void gen7_CmdBeginRenderPass(
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VkCmdBuffer cmdBuffer,
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const VkRenderPassBeginInfo* pRenderPassBegin,
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VkRenderPassContents contents)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
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begin_render_pass(cmd_buffer, pRenderPassBegin);
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gen7_cmd_buffer_begin_subpass(cmd_buffer, pass->subpasses);
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}
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void gen7_CmdNextSubpass(
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VkCmdBuffer cmdBuffer,
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VkRenderPassContents contents)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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assert(cmd_buffer->level == VK_CMD_BUFFER_LEVEL_PRIMARY);
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gen7_cmd_buffer_begin_subpass(cmd_buffer, cmd_buffer->state.subpass + 1);
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}
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void gen7_CmdEndRenderPass(
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VkCmdBuffer cmdBuffer)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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/* Emit a flushing pipe control at the end of a pass. This is kind of a
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* hack but it ensures that render targets always actually get written.
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* Eventually, we should do flushing based on image format transitions
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* or something of that nature.
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*/
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anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
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.PostSyncOperation = NoWrite,
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.RenderTargetCacheFlushEnable = true,
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.InstructionCacheInvalidateEnable = true,
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.DepthCacheFlushEnable = true,
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.VFCacheInvalidationEnable = true,
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.TextureCacheInvalidationEnable = true,
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.CommandStreamerStallEnable = true);
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}
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