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7ae638c0fe
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34355>
256 lines
9.1 KiB
C++
256 lines
9.1 KiB
C++
/*
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* Copyright © 2010 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include "brw_builder.h"
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/*
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* This helper takes a source register and un/shuffles it into the destination
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* register.
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*
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* If source type size is smaller than destination type size the operation
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* needed is a component shuffle. The opposite case would be an unshuffle. If
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* source/destination type size is equal a shuffle is done that would be
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* equivalent to a simple MOV.
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*
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* For example, if source is a 16-bit type and destination is 32-bit. A 3
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* components .xyz 16-bit vector on SIMD8 would be.
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*
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* |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
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* |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
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*
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* This helper will return the following 2 32-bit components with the 16-bit
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* values shuffled:
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*
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* |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
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* |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
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*
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* For unshuffle, the example would be the opposite, a 64-bit type source
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* and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
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* would be:
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*
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* | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
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* | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
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* | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
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* | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
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*
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* The returned result would be the following 4 32-bit components unshuffled:
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*
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* | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
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* | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
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* | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
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* | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
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*
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* - Source and destination register must not be overlapped.
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* - components units are measured in terms of the smaller type between
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* source and destination because we are un/shuffling the smaller
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* components from/into the bigger ones.
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* - first_component parameter allows skipping source components.
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*/
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static void
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shuffle_src_to_dst(const brw_builder &bld,
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const brw_reg &dst,
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const brw_reg &src,
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uint32_t first_component,
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uint32_t components)
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{
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if (brw_type_size_bytes(src.type) == brw_type_size_bytes(dst.type)) {
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assert(!regions_overlap(dst,
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brw_type_size_bytes(dst.type) * bld.dispatch_width() * components,
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offset(src, bld, first_component),
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brw_type_size_bytes(src.type) * bld.dispatch_width() * components));
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for (unsigned i = 0; i < components; i++) {
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bld.MOV(retype(offset(dst, bld, i), src.type),
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offset(src, bld, i + first_component));
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}
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} else if (brw_type_size_bytes(src.type) < brw_type_size_bytes(dst.type)) {
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/* Source is shuffled into destination */
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unsigned size_ratio = brw_type_size_bytes(dst.type) / brw_type_size_bytes(src.type);
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assert(!regions_overlap(dst,
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brw_type_size_bytes(dst.type) * bld.dispatch_width() *
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DIV_ROUND_UP(components, size_ratio),
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offset(src, bld, first_component),
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brw_type_size_bytes(src.type) * bld.dispatch_width() * components));
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brw_reg_type shuffle_type =
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brw_type_with_size(BRW_TYPE_D, brw_type_size_bits(src.type));
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for (unsigned i = 0; i < components; i++) {
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brw_reg shuffle_component_i =
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subscript(offset(dst, bld, i / size_ratio),
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shuffle_type, i % size_ratio);
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bld.MOV(shuffle_component_i,
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retype(offset(src, bld, i + first_component), shuffle_type));
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}
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} else {
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/* Source is unshuffled into destination */
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unsigned size_ratio = brw_type_size_bytes(src.type) / brw_type_size_bytes(dst.type);
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assert(!regions_overlap(dst,
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brw_type_size_bytes(dst.type) * bld.dispatch_width() * components,
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offset(src, bld, first_component / size_ratio),
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brw_type_size_bytes(src.type) * bld.dispatch_width() *
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DIV_ROUND_UP(components + (first_component % size_ratio),
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size_ratio)));
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brw_reg_type shuffle_type =
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brw_type_with_size(BRW_TYPE_D, brw_type_size_bits(dst.type));
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for (unsigned i = 0; i < components; i++) {
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brw_reg shuffle_component_i =
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subscript(offset(src, bld, (first_component + i) / size_ratio),
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shuffle_type, (first_component + i) % size_ratio);
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bld.MOV(retype(offset(dst, bld, i), shuffle_type),
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shuffle_component_i);
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}
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}
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}
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void
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brw_builder::shuffle_from_32bit_read(const brw_reg &dst,
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const brw_reg &src,
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uint32_t first_component,
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uint32_t components) const
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{
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assert(brw_type_size_bytes(src.type) == 4);
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/* This function takes components in units of the destination type while
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* shuffle_src_to_dst takes components in units of the smallest type
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*/
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if (brw_type_size_bytes(dst.type) > 4) {
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assert(brw_type_size_bytes(dst.type) == 8);
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first_component *= 2;
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components *= 2;
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}
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shuffle_src_to_dst(*this, dst, src, first_component, components);
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}
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/**
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* Get the mask of SIMD channels enabled during dispatch and not yet disabled
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* by discard. Due to the layout of the sample mask in the fragment shader
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* thread payload, \p bld is required to have a dispatch_width() not greater
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* than 16 for fragment shaders.
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*/
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brw_reg
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brw_sample_mask_reg(const brw_builder &bld)
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{
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const brw_shader &s = *bld.shader;
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if (s.stage != MESA_SHADER_FRAGMENT) {
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return brw_imm_ud(0xffffffff);
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} else if (s.devinfo->ver >= 20 ||
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brw_wm_prog_data(s.prog_data)->uses_kill) {
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return brw_flag_subreg(sample_mask_flag_subreg(s) + bld.group() / 16);
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} else {
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assert(bld.dispatch_width() <= 16);
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assert(s.devinfo->ver < 20);
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return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7),
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BRW_TYPE_UW);
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}
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}
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/**
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* Predicate the specified instruction on the sample mask.
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*/
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void
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brw_emit_predicate_on_sample_mask(const brw_builder &bld, brw_inst *inst)
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{
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assert(bld.shader->stage == MESA_SHADER_FRAGMENT &&
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bld.group() == inst->group &&
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bld.dispatch_width() == inst->exec_size);
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const brw_shader &s = *bld.shader;
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const brw_reg sample_mask = brw_sample_mask_reg(bld);
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const unsigned subreg = sample_mask_flag_subreg(s);
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if (s.devinfo->ver >= 20 || brw_wm_prog_data(s.prog_data)->uses_kill) {
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assert(sample_mask.file == ARF &&
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sample_mask.nr == brw_flag_subreg(subreg).nr &&
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sample_mask.subnr == brw_flag_subreg(
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subreg + inst->group / 16).subnr);
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} else {
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bld.uniform().MOV(brw_flag_subreg(subreg + inst->group / 16),
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sample_mask);
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}
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if (inst->predicate) {
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assert(inst->predicate == BRW_PREDICATE_NORMAL);
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assert(!inst->predicate_inverse);
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assert(inst->flag_subreg == 0);
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assert(s.devinfo->ver < 20);
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/* Combine the sample mask with the existing predicate by using a
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* vertical predication mode.
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*/
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inst->predicate = BRW_PREDICATE_ALIGN1_ALLV;
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} else {
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inst->flag_subreg = subreg;
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inst->predicate = BRW_PREDICATE_NORMAL;
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inst->predicate_inverse = false;
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}
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}
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brw_reg
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brw_fetch_payload_reg(const brw_builder &bld, uint8_t regs[2],
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brw_reg_type type, unsigned n)
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{
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if (!regs[0])
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return brw_reg();
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if (bld.dispatch_width() > 16) {
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const brw_reg tmp = bld.vgrf(type, n);
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const brw_builder hbld = bld.exec_all().group(16, 0);
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const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
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brw_reg *const components = new brw_reg[m * n];
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for (unsigned c = 0; c < n; c++) {
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for (unsigned g = 0; g < m; g++)
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components[c * m + g] =
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offset(retype(brw_vec8_grf(regs[g], 0), type), hbld, c);
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}
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hbld.LOAD_PAYLOAD(tmp, components, m * n, 0);
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delete[] components;
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return tmp;
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} else {
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return brw_reg(retype(brw_vec8_grf(regs[0], 0), type));
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}
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}
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brw_reg
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brw_fetch_barycentric_reg(const brw_builder &bld, uint8_t regs[2])
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{
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if (!regs[0])
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return brw_reg();
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else if (bld.shader->devinfo->ver >= 20)
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return brw_fetch_payload_reg(bld, regs, BRW_TYPE_F, 2);
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const brw_reg tmp = bld.vgrf(BRW_TYPE_F, 2);
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const brw_builder hbld = bld.exec_all().group(8, 0);
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const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
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brw_reg *const components = new brw_reg[2 * m];
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for (unsigned c = 0; c < 2; c++) {
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for (unsigned g = 0; g < m; g++)
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components[c * m + g] = offset(brw_vec8_grf(regs[g / 2], 0),
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hbld, c + 2 * (g % 2));
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}
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hbld.LOAD_PAYLOAD(tmp, components, 2 * m, 0);
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delete[] components;
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return tmp;
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}
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void
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brw_check_dynamic_msaa_flag(const brw_builder &bld,
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const struct brw_wm_prog_data *wm_prog_data,
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enum intel_msaa_flags flag)
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{
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brw_inst *inst = bld.AND(bld.null_reg_ud(),
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brw_dynamic_msaa_flags(wm_prog_data),
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brw_imm_ud(flag));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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}
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