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dadc50add5
When the SIMD16 Gen4-5 fragment shader payload contains source depth
(g2-3), destination stencil (g4), and destination depth (g5-6), the
single register of stencil makes the destination depth unaligned.
We were generating this instruction in the RT write payload setup:
mov(16) m14<1>F g5<8,8,1>F { align1 compr };
which is illegal, instructions with a source region spanning more than
one register need to be aligned to even registers. This is because the
hardware implicitly does (nr | 1) instead of (nr + 1) when splitting the
compressed instruction into two mov(8)'s.
I believe this would cause the hardware to load g5 twice, replicating
subspan 0-1's destination depth to subspan 2-3. This showed up as 2x2
artifact blocks in both TIS-100 and Reicast.
Normally, we rely on the register allocator to even-align our virtual
GRFs. But we don't control the payload, so we need to lower SIMD widths
to make it work. To fix this, we teach lower_simd_width about the
restriction, and then call it again after lower_load_payload (which is
what generates the offending MOV).
Fixes:
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|---|---|---|
| .. | ||
| amd | ||
| broadcom | ||
| compiler | ||
| egl | ||
| gallium | ||
| gbm | ||
| getopt | ||
| glx | ||
| gtest | ||
| hgl | ||
| intel | ||
| loader | ||
| mapi | ||
| mesa | ||
| util | ||
| vulkan | ||
| git_sha1.h.in | ||
| Makefile.am | ||
| meson.build | ||
| SConscript | ||