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cbf0a38fa4
config -> cfg uconfig -> ucfg context -> ctx Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39680>
238 lines
12 KiB
C
238 lines
12 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_CS_H
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#define RADV_CS_H
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#include <assert.h>
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#include <stdint.h>
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#include <string.h>
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#include "radv_cmd_buffer.h"
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#include "radv_radeon_winsys.h"
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#include "radv_sdma.h"
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#include "sid.h"
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#include "ac_cmdbuf_cp.h"
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#include "ac_cmdbuf_sdma.h"
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static inline unsigned
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radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned needed)
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{
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assert(cs->cdw <= cs->reserved_dw);
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if (cs->max_dw - cs->cdw < needed)
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ws->cs_grow(cs, needed);
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cs->reserved_dw = MAX2(cs->reserved_dw, cs->cdw + needed);
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return cs->cdw + needed;
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}
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#define radeon_begin(cs) \
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struct radv_cmd_stream *__rcs = (cs); \
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ac_cmdbuf_begin(__rcs->b);
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#define radeon_end() ac_cmdbuf_end()
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#define radeon_emit(value) ac_cmdbuf_emit(value)
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#define radeon_emit_array(values, num) ac_cmdbuf_emit_array(values, num)
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/* Packet building helpers for CONFIG registers. */
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#define radeon_set_config_reg_seq(reg, num) ac_cmdbuf_set_cfg_reg_seq(reg, num)
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#define radeon_set_config_reg(reg, value) ac_cmdbuf_set_cfg_reg(reg, value)
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/* Packet building helpers for CONTEXT registers. */
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#define radeon_set_context_reg_seq(reg, num) ac_cmdbuf_set_ctx_reg_seq(reg, num)
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#define radeon_set_context_reg(reg, value) ac_cmdbuf_set_ctx_reg(reg, value)
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#define radeon_set_context_reg_idx(reg, idx, value) ac_cmdbuf_set_ctx_reg_idx(reg, idx, value)
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#define radeon_opt_set_context_reg(reg, reg_enum, value) \
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do { \
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struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
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ac_cmdbuf_opt_set_ctx_reg(__tracked_regs, reg, reg_enum, value); \
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} while (0)
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#define radeon_opt_set_context_reg2(reg, reg_enum, v1, v2) \
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do { \
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struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
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ac_cmdbuf_opt_set_ctx_reg2(__tracked_regs, reg, reg_enum, v1, v2); \
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} while (0)
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#define radeon_opt_set_context_reg3(reg, reg_enum, v1, v2, v3) \
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do { \
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struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
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ac_cmdbuf_opt_set_ctx_reg3(__tracked_regs, reg, reg_enum, v1, v2, v3); \
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} while (0)
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#define radeon_opt_set_context_reg4(reg, reg_enum, v1, v2, v3, v4) \
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do { \
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struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
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ac_cmdbuf_opt_set_ctx_reg4(__tracked_regs, reg, reg_enum, v1, v2, v3, v4); \
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} while (0)
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#define radeon_opt_set_context_regn(reg, values, saved_values, num) \
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ac_cmdbuf_opt_set_ctx_regn(reg, values, saved_values, num)
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/* Packet building helpers for SH registers. */
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#define radeon_set_sh_reg_seq(reg, num) ac_cmdbuf_set_sh_reg_seq(reg, num)
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#define radeon_set_sh_reg(reg, value) ac_cmdbuf_set_sh_reg(reg, value)
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#define radeon_set_sh_reg_idx(info, reg, idx, value) ac_cmdbuf_set_sh_reg_idx(info, reg, idx, value)
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/* Packet building helpers for UCONFIG registers. */
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#define radeon_set_uconfig_reg_seq(reg, num) ac_cmdbuf_set_ucfg_reg_seq(reg, num)
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#define radeon_set_uconfig_reg(reg, value) ac_cmdbuf_set_ucfg_reg(reg, value)
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#define radeon_set_uconfig_reg_idx(info, reg, idx, value) ac_cmdbuf_set_ucfg_reg_idx(info, reg, idx, value)
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#define radeon_set_uconfig_perfctr_reg_seq(gfx_level, ip_type, reg, num) \
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ac_cmdbuf_set_ucfg_perfctr_reg_seq(gfx_level, ip_type, reg, num)
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#define radeon_set_uconfig_perfctr_reg(gfx_level, ip_type, reg, value) \
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ac_cmdbuf_set_ucfg_perfctr_reg(gfx_level, ip_type, reg, value)
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#define radeon_set_privileged_config_reg(reg, value) ac_cmdbuf_set_privileged_cfg_reg(reg, value)
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#define radeon_event_write_predicate(event_type, predicate) ac_cmdbuf_event_write_predicate(event_type, predicate)
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#define radeon_event_write(event_type) ac_cmdbuf_event_write(event_type)
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#define radeon_emit_32bit_pointer(sh_offset, va, info) ac_cmdbuf_emit_32bit_pointer(sh_offset, va, info)
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#define radeon_emit_64bit_pointer(sh_offset, va) ac_cmdbuf_emit_64bit_pointer(sh_offset, va)
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/* GFX12 packet building helpers for PAIRS packets. */
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#define gfx12_begin_context_regs() ac_gfx12_begin_ctx_regs()
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#define gfx12_set_context_reg(reg, value) ac_gfx12_set_ctx_reg(reg, value)
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#define gfx12_opt_set_context_reg(reg, reg_enum, value) \
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do { \
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struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
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ac_gfx12_opt_set_reg(__tracked_regs, reg, reg_enum, value, SI_CONTEXT_REG_OFFSET); \
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} while (0)
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#define gfx12_opt_set_context_reg2(reg, reg_enum, v1, v2) \
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do { \
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struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
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ac_gfx12_opt_set_reg2(__tracked_regs, reg, reg_enum, v1, v2, SI_CONTEXT_REG_OFFSET); \
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} while (0)
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#define gfx12_end_context_regs() ac_gfx12_end_ctx_regs()
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/* GFX12 packet building helpers for buffered registers. */
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#define gfx12_push_sh_reg(reg, value) ac_gfx12_push_sh_reg(__rcs->buffered_sh_regs, reg, value)
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#define gfx12_push_32bit_pointer(sh_offset, va, info) \
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ac_gfx12_push_32bit_pointer(__rcs->buffered_sh_regs, sh_offset, va, info)
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#define gfx12_push_64bit_pointer(sh_offset, va) ac_gfx12_push_64bit_pointer(__rcs->buffered_sh_regs, sh_offset, va)
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/* GFX11 packet building helpers for PAIRS packets. */
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#define gfx11_begin_packed_context_regs() ac_gfx11_begin_packed_ctx_regs()
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#define gfx11_set_context_reg(reg, value) ac_gfx11_set_ctx_reg(reg, value)
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#define gfx11_end_packed_context_regs() ac_gfx11_end_packed_ctx_regs()
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#define gfx11_opt_set_context_reg(reg, reg_enum, value) \
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do { \
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struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
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ac_gfx11_opt_set_ctx_reg(__tracked_regs, reg, reg_enum, value); \
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} while (0)
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#define gfx11_opt_set_context_reg2(reg, reg_enum, v1, v2) \
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do { \
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struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
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ac_gfx11_opt_set_ctx_reg2(__tracked_regs, reg, reg_enum, v1, v2); \
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} while (0)
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ALWAYS_INLINE static void
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radv_gfx12_emit_buffered_regs(const struct radv_device *device, struct radv_cmd_stream *cs)
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{
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const uint32_t reg_count = cs->buffered_sh_regs.num;
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if (!reg_count)
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return;
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radeon_check_space(device->ws, cs->b, 1 + reg_count * 2);
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radeon_begin(cs);
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radeon_emit(PKT3(PKT3_SET_SH_REG_PAIRS, reg_count * 2 - 1, 0) | PKT3_RESET_FILTER_CAM_S(1));
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radeon_emit_array(cs->buffered_sh_regs.gfx12.regs, reg_count * 2);
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radeon_end();
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cs->buffered_sh_regs.num = 0;
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}
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ALWAYS_INLINE static void
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radv_cp_wait_mem(struct radv_cmd_stream *cs, const uint32_t op, const uint64_t va, const uint32_t ref,
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const uint32_t mask)
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{
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assert(op == WAIT_REG_MEM_EQUAL || op == WAIT_REG_MEM_NOT_EQUAL || op == WAIT_REG_MEM_GREATER_OR_EQUAL);
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if (cs->hw_ip == AMD_IP_GFX || cs->hw_ip == AMD_IP_COMPUTE) {
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ac_emit_cp_wait_mem(cs->b, va, ref, mask, op);
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} else if (cs->hw_ip == AMD_IP_SDMA) {
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ac_emit_sdma_wait_mem(cs->b, op, va, ref, mask);
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} else {
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UNREACHABLE("unsupported queue family");
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}
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}
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ALWAYS_INLINE static unsigned
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radv_cs_write_data_head(const struct radv_device *device, struct radv_cmd_stream *cs, const unsigned engine_sel,
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const uint64_t va, const unsigned count, const bool predicating)
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{
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/* Return the correct cdw at the end of the packet so the caller can assert it. */
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const unsigned cdw_end = radeon_check_space(device->ws, cs->b, 4 + count);
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if (cs->hw_ip == AMD_IP_COMPUTE || cs->hw_ip == AMD_IP_GFX) {
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ac_emit_cp_write_data_head(cs->b, engine_sel, V_370_MEM, va, count, predicating);
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} else if (cs->hw_ip == AMD_IP_SDMA) {
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ac_emit_sdma_write_data_head(cs->b, va, count);
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} else {
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UNREACHABLE("unsupported queue family");
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}
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return cdw_end;
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}
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ALWAYS_INLINE static void
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radv_cs_write_data(const struct radv_device *device, struct radv_cmd_stream *cs, const unsigned engine_sel,
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const uint64_t va, const unsigned count, const uint32_t *dwords, const bool predicating)
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{
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ASSERTED const unsigned cdw_end = radv_cs_write_data_head(device, cs, engine_sel, va, count, predicating);
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radeon_begin(cs);
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radeon_emit_array(dwords, count);
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radeon_end();
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assert(cs->b->cdw == cdw_end);
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}
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void radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, unsigned event,
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unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
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uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va);
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void radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level,
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uint32_t *flush_cnt, uint64_t flush_va, enum radv_cmd_flush_bits flush_bits,
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enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va);
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VkResult radv_create_cmd_stream(const struct radv_device *device, const enum amd_ip_type ip_type,
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const bool is_secondary, struct radv_cmd_stream **cs_out);
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void radv_init_cmd_stream(const struct radv_device *device, struct radv_cmd_stream *cs, const enum amd_ip_type ip_type);
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void radv_reset_cmd_stream(const struct radv_device *device, struct radv_cmd_stream *cs);
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VkResult radv_finalize_cmd_stream(const struct radv_device *device, struct radv_cmd_stream *cs);
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void radv_destroy_cmd_stream(const struct radv_device *device, struct radv_cmd_stream *cs);
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#endif /* RADV_CS_H */
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