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04777171e0
This helps a lot with accessing surface handles in control flow. Our resource_intel intrinsic has a non_uniform flag, in which case we cannot apply this optimization. But in uniform cases, this is just a massive win. We drop all kind of pipeline stalls due to find_live_channel. We also reduce register pressure by doing the surface handle computation in a single GRF (instead of 2 or 4). There are some regressions in max dispatch width but those I think are only on SIMD32 and due to the current heuristic disabling it after throughput comparison with SIMD16. We know this heuristic is not perfect, it should probably be updated in another change. Here are some stats (all titles seem to have similar gains) : PERCENTAGE DELTAS Shaders Instrs Cycles Subgroup size Send messages Spill count Fill count Scratch Memory Size Max live registers Max dispatch width red_dead_redemption2 5860 -36.80% -5.67% +0.77% +0.06% -81.26% -79.16% -70.62% -8.63% -6.93% --------------------------------------------------------------------------------------------------------------------------------------------------------------- All affected 4716 -37.29% -5.67% +0.95% +0.07% -81.26% -79.16% -70.62% -9.15% -8.47% --------------------------------------------------------------------------------------------------------------------------------------------------------------- Total 5860 -36.80% -5.67% +0.77% +0.06% -81.26% -79.16% -70.62% -8.63% -6.93% PERCENTAGE DELTAS Shaders Instrs Cycles Subgroup size Send messages Spill count Fill count Scratch Memory Size Max live registers Max dispatch width rise_of_the_tomb_raider_g2 12010 -37.19% -22.12% +0.01% +0.00% -99.01% -99.14% -98.65% -7.62% -4.96% --------------------------------------------------------------------------------------------------------------------------------------------------------------------- All affected 11732 -37.27% -22.14% +0.01% +0.00% -99.01% -99.14% -98.65% -7.67% -5.11% --------------------------------------------------------------------------------------------------------------------------------------------------------------------- Total 12010 -37.19% -22.12% +0.01% +0.00% -99.01% -99.14% -98.65% -7.62% -4.96% PERCENTAGE DELTAS Shaders Instrs Cycles Spill count Fill count Scratch Memory Size Max live registers Max dispatch width total_war_warhammer2 462 -27.45% -12.42% -82.35% -88.46% -66.67% -5.52% -5.62% ----------------------------------------------------------------------------------------------------------------------------------- All affected 335 -28.31% -12.77% -82.35% -88.46% -66.67% -6.25% -7.24% ----------------------------------------------------------------------------------------------------------------------------------- Total 462 -27.45% -12.42% -82.35% -88.46% -66.67% -5.52% -5.62% PERCENTAGE DELTAS Shaders Instrs Cycles Subgroup size Send messages Spill count Fill count Scratch Memory Size Max live registers Max dispatch width witcher_3_dxvk_g2 1049 -36.94% -57.82% +0.06% +0.01% -98.52% -97.29% -98.10% -7.81% -1.00% ------------------------------------------------------------------------------------------------------------------------------------------------------------ All affected 693 -41.93% -58.45% +0.09% +0.01% -98.52% -97.29% -98.10% -10.25% -1.33% ------------------------------------------------------------------------------------------------------------------------------------------------------------ Total 1049 -36.94% -57.82% +0.06% +0.01% -98.52% -97.29% -98.10% -7.81% -1.00% Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21645> |
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| .. | ||
| brw_cfg.cpp | ||
| brw_cfg.h | ||
| brw_clip.h | ||
| brw_clip_line.c | ||
| brw_clip_point.c | ||
| brw_clip_tri.c | ||
| brw_clip_unfilled.c | ||
| brw_clip_util.c | ||
| brw_compile_clip.c | ||
| brw_compile_ff_gs.c | ||
| brw_compile_sf.c | ||
| brw_compiler.c | ||
| brw_compiler.h | ||
| brw_dead_control_flow.cpp | ||
| brw_dead_control_flow.h | ||
| brw_debug_recompile.c | ||
| brw_disasm.c | ||
| brw_disasm_info.c | ||
| brw_disasm_info.h | ||
| brw_eu.c | ||
| brw_eu.h | ||
| brw_eu_compact.c | ||
| brw_eu_defines.h | ||
| brw_eu_emit.c | ||
| brw_eu_util.c | ||
| brw_eu_validate.c | ||
| brw_fs.cpp | ||
| brw_fs.h | ||
| brw_fs_bank_conflicts.cpp | ||
| brw_fs_builder.h | ||
| brw_fs_cmod_propagation.cpp | ||
| brw_fs_combine_constants.cpp | ||
| brw_fs_copy_propagation.cpp | ||
| brw_fs_cse.cpp | ||
| brw_fs_dead_code_eliminate.cpp | ||
| brw_fs_generator.cpp | ||
| brw_fs_live_variables.cpp | ||
| brw_fs_live_variables.h | ||
| brw_fs_lower_pack.cpp | ||
| brw_fs_lower_regioning.cpp | ||
| brw_fs_nir.cpp | ||
| brw_fs_reg_allocate.cpp | ||
| brw_fs_register_coalesce.cpp | ||
| brw_fs_saturate_propagation.cpp | ||
| brw_fs_scoreboard.cpp | ||
| brw_fs_sel_peephole.cpp | ||
| brw_fs_thread_payload.cpp | ||
| brw_fs_validate.cpp | ||
| brw_fs_visitor.cpp | ||
| brw_gfx_ver_enum.h | ||
| brw_inst.h | ||
| brw_interpolation_map.c | ||
| brw_ir.h | ||
| brw_ir_allocator.h | ||
| brw_ir_analysis.h | ||
| brw_ir_fs.h | ||
| brw_ir_performance.cpp | ||
| brw_ir_performance.h | ||
| brw_ir_vec4.h | ||
| brw_isa_info.h | ||
| brw_kernel.c | ||
| brw_kernel.h | ||
| brw_lower_logical_sends.cpp | ||
| brw_mesh.cpp | ||
| brw_nir.c | ||
| brw_nir.h | ||
| brw_nir_analyze_boolean_resolves.c | ||
| brw_nir_analyze_ubo_ranges.c | ||
| brw_nir_attribute_workarounds.c | ||
| brw_nir_blockify_uniform_loads.c | ||
| brw_nir_clamp_image_1d_2d_array_sizes.c | ||
| brw_nir_clamp_per_vertex_loads.c | ||
| brw_nir_lower_alpha_to_coverage.c | ||
| brw_nir_lower_conversions.c | ||
| brw_nir_lower_cs_intrinsics.c | ||
| brw_nir_lower_intersection_shader.c | ||
| brw_nir_lower_non_uniform_resource_intel.c | ||
| brw_nir_lower_ray_queries.c | ||
| brw_nir_lower_rt_intrinsics.c | ||
| brw_nir_lower_shader_calls.c | ||
| brw_nir_lower_shading_rate_output.c | ||
| brw_nir_lower_storage_image.c | ||
| brw_nir_opt_peephole_ffma.c | ||
| brw_nir_opt_peephole_imul32x16.c | ||
| brw_nir_rt.c | ||
| brw_nir_rt.h | ||
| brw_nir_rt_builder.h | ||
| brw_nir_tcs_workarounds.c | ||
| brw_nir_trig_workarounds.py | ||
| brw_packed_float.c | ||
| brw_predicated_break.cpp | ||
| brw_prim.h | ||
| brw_private.h | ||
| brw_reg.h | ||
| brw_reg_type.c | ||
| brw_reg_type.h | ||
| brw_rt.h | ||
| brw_schedule_instructions.cpp | ||
| brw_shader.cpp | ||
| brw_shader.h | ||
| brw_simd_selection.cpp | ||
| brw_vec4.cpp | ||
| brw_vec4.h | ||
| brw_vec4_builder.h | ||
| brw_vec4_cmod_propagation.cpp | ||
| brw_vec4_copy_propagation.cpp | ||
| brw_vec4_cse.cpp | ||
| brw_vec4_dead_code_eliminate.cpp | ||
| brw_vec4_generator.cpp | ||
| brw_vec4_gs_nir.cpp | ||
| brw_vec4_gs_visitor.cpp | ||
| brw_vec4_gs_visitor.h | ||
| brw_vec4_live_variables.cpp | ||
| brw_vec4_live_variables.h | ||
| brw_vec4_nir.cpp | ||
| brw_vec4_reg_allocate.cpp | ||
| brw_vec4_surface_builder.cpp | ||
| brw_vec4_surface_builder.h | ||
| brw_vec4_tcs.cpp | ||
| brw_vec4_tcs.h | ||
| brw_vec4_tes.cpp | ||
| brw_vec4_tes.h | ||
| brw_vec4_visitor.cpp | ||
| brw_vec4_vs.h | ||
| brw_vec4_vs_visitor.cpp | ||
| brw_vue_map.c | ||
| gfx6_gs_visitor.cpp | ||
| gfx6_gs_visitor.h | ||
| intel_clc.c | ||
| meson.build | ||
| test_eu_compact.cpp | ||
| test_eu_validate.cpp | ||
| test_fs_cmod_propagation.cpp | ||
| test_fs_copy_propagation.cpp | ||
| test_fs_saturate_propagation.cpp | ||
| test_fs_scoreboard.cpp | ||
| test_simd_selection.cpp | ||
| test_vec4_cmod_propagation.cpp | ||
| test_vec4_copy_propagation.cpp | ||
| test_vec4_dead_code_eliminate.cpp | ||
| test_vec4_register_coalesce.cpp | ||
| test_vf_float_conversions.cpp | ||