Timur Kristóf d004b4929d radv: Don't assume there is always at least 1 preamble. ... This fixes a mistake which assumes there is always at least 1 preamble. This assumption is currently incorrect on transfer queues. Fixes: e10b2f273e Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20401>		2022-12-21 09:39:37 +01:00
..
addrlib	meson: Enable initialized-but-unused warning for MSVC	2022-11-17 21:20:38 +00:00
ci	radv: Enable EXT_mesh_shader by default on GFX10.3.	2022-12-20 14:23:49 +00:00
common	ac: Add has_gang_submit field to ac_gpu_info.	2022-12-20 14:23:49 +00:00
compiler	aco/gfx11: implement load_input_vertex	2022-12-16 17:45:34 +00:00
drm-shim	r300: use drm_shim_override	2022-11-16 14:37:47 +00:00
llvm	ac/llvm: remove deref image/texture code	2022-12-19 09:22:45 +08:00
registers	amd/registers: regenerate gfx11 headers from amd-staging-drm-next	2022-11-04 00:42:08 +00:00
vulkan	radv: Don't assume there is always at least 1 preamble.	2022-12-21 09:39:37 +01:00
.clang-format	radv: Add nir_foreach_variable_with_modes to .clang-format	2022-12-09 07:07:10 +00:00
meson.build	meson: build radeon drm-shim also for r300 and r600	2022-11-16 14:37:47 +00:00