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cd6c4bf772
We never read this member, so let's cull it. Acked-by: Ashish Chauhan <Ashish.Chauhan@imgtec.com> Acked-by: Frank Binns <frank.binns@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38832>
348 lines
13 KiB
C
348 lines
13 KiB
C
/*
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* Copyright © 2022 Imagination Technologies Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef PVR_FORMATS_H
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#define PVR_FORMATS_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <vulkan/vulkan.h>
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#include "util/format/u_formats.h"
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#include "vk_format.h"
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/* This is based on VkClearColorValue which is an array of RGBA, and on the
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* output register usage for the biggest 32 bit 4 component formats which use up
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* all 4 output registers.
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* So this can be used for both unpacked RGBA value and to represent values
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* packed according to the hardware (the accum format).
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*/
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#define PVR_CLEAR_COLOR_ARRAY_SIZE 4
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#define PVR_TEX_FORMAT_COUNT (ROGUE_TEXSTATE_IMAGE_WORD0_TEXFORMAT_MAX_SIZE + 1)
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enum pvr_pbe_accum_format {
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PVR_PBE_ACCUM_FORMAT_INVALID = 0, /* Explicitly treat 0 as invalid. */
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PVR_PBE_ACCUM_FORMAT_U8,
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PVR_PBE_ACCUM_FORMAT_S8,
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PVR_PBE_ACCUM_FORMAT_U16,
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PVR_PBE_ACCUM_FORMAT_S16,
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PVR_PBE_ACCUM_FORMAT_F16,
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PVR_PBE_ACCUM_FORMAT_F32,
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PVR_PBE_ACCUM_FORMAT_UINT8,
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PVR_PBE_ACCUM_FORMAT_UINT16,
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PVR_PBE_ACCUM_FORMAT_UINT32,
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PVR_PBE_ACCUM_FORMAT_SINT8,
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PVR_PBE_ACCUM_FORMAT_SINT16,
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PVR_PBE_ACCUM_FORMAT_SINT32,
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/* Formats with medp shader output precision. */
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PVR_PBE_ACCUM_FORMAT_UINT32_MEDP,
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PVR_PBE_ACCUM_FORMAT_SINT32_MEDP,
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PVR_PBE_ACCUM_FORMAT_U1010102,
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PVR_PBE_ACCUM_FORMAT_U24,
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};
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/**
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* Pixel related shader selector. The logic selecting the shader has to take
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* into account the pixel related properties (controlling the conversion path in
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* the shader) and the geometry related properties (controlling the sample
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* position calcs). These two can be orthogonal.
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*
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* integer format conversions, bit depth : 8, 16, 32 per ch formats : signed,
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* unsigned. Strategy: convert everything to U32 or S32 then USC pack. PBE just
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* pass through.
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*
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* fixed point format conversions, bit depth 565, 1555, 555 etc. Strategy:
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* fcnorm to 4 F32, then USC pack to F16F16. PBE converts to destination
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*
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* float/fixed format conversions
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* strategy: fcnorm, then pack to f16 _when_ destination is not f32.
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* fmt | unorm | flt |
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* 8 | x | |
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* 16 | x | x |
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* 32 | x | x |
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*
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*
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* non-merge type DS blit table
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* **********************************************
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* * * S8 D16 D24S8 D32 D32S8 *
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* **********************************************
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* * S8 * cpy i i i i *
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* * D16 * i cpy i - i *
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* * D24S8 * swiz - cpy (1) - *
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* * D32 * i - i cpy i *
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* * D32S8 * (2) - - cpy cpy *
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* **********************************************
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*
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* merge with stencil pick type DS blit table
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* **********************************************
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* * * S8 D16 D24S8 D32 D32S8 *
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* **********************************************
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* * S8 * i i (1) i (2) *
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* * D16 * i i i i i *
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* * D24S8 * i i (3) i (4) *
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* * D32 * i i i i i *
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* * D32S8 * i i (5) i (6) *
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* **********************************************
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*
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* merge with depth pick type DS blit table
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* **********************************************
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* * * S8 D16 D24S8 D32 D32S8 *
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* **********************************************
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* * S8 * i i i i i *
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* * D16 * - - - - - *
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* * D24S8 * - - (s) - - *
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* * D32 * - - (1) - (2) *
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* * D32S8 * - - - - (s) *
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* **********************************************
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*
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* D formats are unpacked into a single register according to their format
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* S formats are unpacked into a single register in U8
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* D24S8 is in a single 32 bit register (as the PBE can't read it from
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* unpacked.)
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*
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* Swizzles are applied on the TPU not the PBE because of potential
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* accumulation i.e. a non-iterated shader doesn't know if it writes the output
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* buffer for PBE emit or a second pass blend.
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*/
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enum pvr_transfer_pbe_pixel_src {
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PVR_TRANSFER_PBE_PIXEL_SRC_UU8888 = 0,
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PVR_TRANSFER_PBE_PIXEL_SRC_US8888 = 1,
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PVR_TRANSFER_PBE_PIXEL_SRC_UU16U16 = 2,
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PVR_TRANSFER_PBE_PIXEL_SRC_US16S16 = 3,
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PVR_TRANSFER_PBE_PIXEL_SRC_SU8888 = 4,
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PVR_TRANSFER_PBE_PIXEL_SRC_SS8888 = 5,
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PVR_TRANSFER_PBE_PIXEL_SRC_SU16U16 = 6,
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PVR_TRANSFER_PBE_PIXEL_SRC_SS16S16 = 7,
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PVR_TRANSFER_PBE_PIXEL_SRC_UU1010102 = 8,
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PVR_TRANSFER_PBE_PIXEL_SRC_SU1010102 = 9,
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PVR_TRANSFER_PBE_PIXEL_SRC_RBSWAP_UU1010102 = 10,
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PVR_TRANSFER_PBE_PIXEL_SRC_RBSWAP_SU1010102 = 11,
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PVR_TRANSFER_PBE_PIXEL_SRC_SU32U32 = 12,
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PVR_TRANSFER_PBE_PIXEL_SRC_S4XU32 = 13,
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PVR_TRANSFER_PBE_PIXEL_SRC_US32S32 = 14,
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PVR_TRANSFER_PBE_PIXEL_SRC_U4XS32 = 15,
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PVR_TRANSFER_PBE_PIXEL_SRC_F16F16 = 16,
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PVR_TRANSFER_PBE_PIXEL_SRC_U16NORM = 17,
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PVR_TRANSFER_PBE_PIXEL_SRC_S16NORM = 18,
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PVR_TRANSFER_PBE_PIXEL_SRC_F32X4 = 19,
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PVR_TRANSFER_PBE_PIXEL_SRC_F32X2 = 20,
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PVR_TRANSFER_PBE_PIXEL_SRC_F32 = 21,
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PVR_TRANSFER_PBE_PIXEL_SRC_RAW32 = 22,
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PVR_TRANSFER_PBE_PIXEL_SRC_RAW64 = 23,
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PVR_TRANSFER_PBE_PIXEL_SRC_RAW128 = 24,
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/* f16 to U8 conversion in shader. */
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PVR_TRANSFER_PBE_PIXEL_SRC_F16_U8 = 25,
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PVR_TRANSFER_PBE_PIXEL_SRC_SWAP_LMSB = 26,
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PVR_TRANSFER_PBE_PIXEL_SRC_MOV_BY45 = 27,
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PVR_TRANSFER_PBE_PIXEL_SRC_D24S8 = 28,
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PVR_TRANSFER_PBE_PIXEL_SRC_S8D24 = 29,
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PVR_TRANSFER_PBE_PIXEL_SRC_D32S8 = 30,
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/* D: D32_S8 */
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PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_S8_D32S8 = 31,
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PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_D24S8_D32S8 = 32,
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PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_D32S8_D32S8 = 33,
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PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D32S8_D32S8 = 34,
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/* D: D32 */
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PVR_TRANSFER_PBE_PIXEL_SRC_CONV_D24_D32 = 35,
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PVR_TRANSFER_PBE_PIXEL_SRC_CONV_D32U_D32F = 36,
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/* D : D24_S8 */
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PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_S8_D24S8 = 37,
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PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_D24S8_D24S8 = 38,
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PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D24S8_D24S8 = 39,
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PVR_TRANSFER_PBE_PIXEL_SRC_CONV_D32_D24S8 = 40,
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PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D32_D24S8 = 41,
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PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D32U_D24S8 = 42,
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/* ob0 holds Y and ob0 holds U or V. */
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PVR_TRANSFER_PBE_PIXEL_SRC_YUV_PACKED = 43,
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/* ob0 holds Y, ob1 holds U, ob2 holds V. */
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PVR_TRANSFER_PBE_PIXEL_SRC_Y_U_V = 44,
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PVR_TRANSFER_PBE_PIXEL_SRC_MASK16 = 45,
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PVR_TRANSFER_PBE_PIXEL_SRC_MASK32 = 46,
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PVR_TRANSFER_PBE_PIXEL_SRC_MASK48 = 47,
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PVR_TRANSFER_PBE_PIXEL_SRC_MASK64 = 48,
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PVR_TRANSFER_PBE_PIXEL_SRC_MASK96 = 49,
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PVR_TRANSFER_PBE_PIXEL_SRC_MASK128 = 50,
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PVR_TRANSFER_PBE_PIXEL_SRC_CONV_S8D24_D24S8 = 51,
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/* ob0 holds Y and ob0 holds V or U. */
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PVR_TRANSFER_PBE_PIXEL_SRC_YVU_PACKED = 52,
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/* ob0 holds Y, ob1 holds UV interleaved. */
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PVR_TRANSFER_PBE_PIXEL_SRC_Y_UV_INTERLEAVED = 53,
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/* FIXME: This changes for other BVNC's which may change the hashing logic
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* in pvr_hash_shader.
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*/
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PVR_TRANSFER_PBE_PIXEL_SRC_NUM = 54,
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};
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/* FIXME: Replace all instances of uint32_t with ROGUE_TEXSTATE_FORMAT or
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* ROGUE_TEXSTATE_FORMAT_COMPRESSED after the pvr_common cleanup is complete.
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*/
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struct pvr_tex_format_description {
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enum pipe_format pipe_format_int;
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enum pipe_format pipe_format_float;
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};
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struct pvr_tex_format_compressed_description {
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uint32_t tex_format;
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enum pipe_format pipe_format;
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uint32_t tex_format_simple;
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};
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bool pvr_tex_format_is_supported(uint32_t tex_format);
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const struct pvr_tex_format_description *
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pvr_get_tex_format_description(uint32_t tex_format);
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#define pvr_foreach_supported_tex_format_(format) \
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for (enum ROGUE_TEXSTATE_FORMAT format = 0; format < PVR_TEX_FORMAT_COUNT; \
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format++) \
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if (pvr_tex_format_is_supported(format))
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#define pvr_foreach_supported_tex_format(format, desc) \
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pvr_foreach_supported_tex_format_ (format) \
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for (const struct pvr_tex_format_description *desc = \
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pvr_get_tex_format_description(format); \
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desc; \
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desc = NULL)
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bool pvr_tex_format_compressed_is_supported(uint32_t tex_format);
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const struct pvr_tex_format_compressed_description *
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pvr_get_tex_format_compressed_description(uint32_t tex_format);
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#define pvr_foreach_supported_tex_format_compressed_(format) \
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for (enum ROGUE_TEXSTATE_FORMAT_COMPRESSED format = 0; \
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format < PVR_TEX_FORMAT_COUNT; \
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format++) \
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if (pvr_tex_format_compressed_is_supported(format))
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#define pvr_foreach_supported_tex_format_compressed(format, desc) \
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pvr_foreach_supported_tex_format_compressed_ (format) \
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for (const struct pvr_tex_format_compressed_description *desc = \
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pvr_get_tex_format_compressed_description(format); \
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desc; \
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desc = NULL)
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struct util_format_description;
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const uint8_t *
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pvr_get_format_swizzle_for_tpu(const struct util_format_description *desc);
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const uint8_t *pvr_get_format_swizzle(VkFormat vk_format);
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uint32_t pvr_get_tex_format(VkFormat vk_format);
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uint32_t pvr_get_tex_format_aspect(VkFormat vk_format,
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VkImageAspectFlags aspect_mask);
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uint32_t pvr_get_pbe_packmode(VkFormat vk_format);
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uint32_t pvr_get_pbe_accum_format(VkFormat vk_format);
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uint32_t pvr_get_pbe_accum_format_size_in_bytes(VkFormat vk_format);
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bool pvr_format_is_pbe_downscalable(const struct pvr_device_info *dev_info,
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VkFormat vk_format);
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void pvr_get_hw_clear_color(VkFormat vk_format,
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VkClearColorValue value,
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uint32_t packed_out[static const 4]);
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uint32_t pvr_pbe_pixel_num_loads(enum pvr_transfer_pbe_pixel_src pbe_format);
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bool pvr_pbe_pixel_is_norm(enum pvr_transfer_pbe_pixel_src pbe_format);
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uint32_t pvr_pbe_pixel_size(enum pvr_transfer_pbe_pixel_src pbe_format);
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static inline bool pvr_vk_format_has_32bit_component(VkFormat vk_format)
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{
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const struct util_format_description *desc =
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vk_format_description(vk_format);
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for (uint32_t i = 0; i < desc->nr_channels; i++) {
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if (desc->channel[i].size == 32U)
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return true;
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}
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return false;
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}
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static inline bool pvr_vk_format_is_fully_normalized(VkFormat vk_format)
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{
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const struct util_format_description *desc =
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vk_format_description(vk_format);
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for (uint32_t i = 0; i < desc->nr_channels; i++) {
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if (!desc->channel[i].normalized)
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return false;
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}
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return true;
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}
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static inline uint32_t
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pvr_vk_format_get_common_color_channel_count(VkFormat src_format,
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VkFormat dst_format)
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{
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const struct util_format_description *dst_desc =
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vk_format_description(dst_format);
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const struct util_format_description *src_desc =
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vk_format_description(src_format);
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uint32_t count = 0;
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/* Check if destination format is alpha only and source format has alpha
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* channel.
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*/
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if (util_format_is_alpha(vk_format_to_pipe_format(dst_format))) {
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count = 1;
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} else if (dst_desc->nr_channels <= src_desc->nr_channels) {
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for (uint32_t i = 0; i < dst_desc->nr_channels; i++) {
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enum pipe_swizzle swizzle = dst_desc->swizzle[i];
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if (swizzle > PIPE_SWIZZLE_W)
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continue;
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for (uint32_t j = 0; j < src_desc->nr_channels; j++) {
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if (src_desc->swizzle[j] == swizzle) {
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count++;
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break;
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}
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}
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}
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} else {
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count = dst_desc->nr_channels;
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}
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return count;
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}
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#endif /* PVR_FORMATS_H */
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