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https://gitlab.freedesktop.org/mesa/mesa.git
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b741a9a851
Set the flag on compute shaders when the application has enabled the cooperative matrix feature. We might still want to enable this only when DPAS is actually used. The current method is based on many suggestions from Lionel. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
372 lines
13 KiB
C
372 lines
13 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "anv_private.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#include "common/intel_l3_config.h"
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/**
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* This file implements some lightweight memcpy/memset operations on the GPU
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* using a vertex buffer and streamout.
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*/
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/**
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* Returns the greatest common divisor of a and b that is a power of two.
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*/
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static uint64_t
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gcd_pow2_u64(uint64_t a, uint64_t b)
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{
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assert(a > 0 || b > 0);
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unsigned a_log2 = ffsll(a) - 1;
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unsigned b_log2 = ffsll(b) - 1;
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/* If either a or b is 0, then a_log2 or b_log2 will be UINT_MAX in which
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* case, the MIN2() will take the other one. If both are 0 then we will
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* hit the assert above.
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*/
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return 1 << MIN2(a_log2, b_log2);
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}
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static void
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emit_common_so_memcpy(struct anv_batch *batch, struct anv_device *device,
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const struct intel_l3_config *l3_config)
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{
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anv_batch_emit(batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
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vfi.InstancingEnable = false;
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vfi.VertexElementIndex = 0;
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}
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anv_batch_emit(batch, GENX(3DSTATE_VF_SGVS), sgvs);
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#if GFX_VER >= 11
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anv_batch_emit(batch, GENX(3DSTATE_VF_SGVS_2), sgvs);
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#endif
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/* Disable all shader stages */
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anv_batch_emit(batch, GENX(3DSTATE_VS), vs);
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anv_batch_emit(batch, GENX(3DSTATE_HS), hs);
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anv_batch_emit(batch, GENX(3DSTATE_TE), te);
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anv_batch_emit(batch, GENX(3DSTATE_DS), DS);
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anv_batch_emit(batch, GENX(3DSTATE_GS), gs);
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anv_batch_emit(batch, GENX(3DSTATE_PS), gs);
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#if GFX_VERx10 >= 125
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/* Disable Mesh, we can't have this and streamout enabled at the same
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* time.
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*/
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if (device->vk.enabled_extensions.EXT_mesh_shader) {
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anv_batch_emit(batch, GENX(3DSTATE_MESH_CONTROL), mesh);
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anv_batch_emit(batch, GENX(3DSTATE_TASK_CONTROL), task);
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}
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/* Wa_16013994831 - Disable preemption during streamout. */
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if (intel_needs_workaround(device->info, 16013994831))
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genX(batch_set_preemption)(batch, device->info, _3D, false);
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#endif
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anv_batch_emit(batch, GENX(3DSTATE_SBE), sbe) {
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sbe.VertexURBEntryReadOffset = 1;
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sbe.NumberofSFOutputAttributes = 1;
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sbe.VertexURBEntryReadLength = 1;
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sbe.ForceVertexURBEntryReadLength = true;
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sbe.ForceVertexURBEntryReadOffset = true;
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for (unsigned i = 0; i < 32; i++)
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sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
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}
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/* Emit URB setup. We tell it that the VS is active because we want it to
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* allocate space for the VS. Even though one isn't run, we need VUEs to
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* store the data that VF is going to pass to SOL.
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*/
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const unsigned entry_size[4] = { DIV_ROUND_UP(32, 64), 1, 1, 1 };
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genX(emit_urb_setup)(device, batch, l3_config,
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VK_SHADER_STAGE_VERTEX_BIT, entry_size, NULL);
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#if GFX_VER >= 12
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/* Disable Primitive Replication. */
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anv_batch_emit(batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr);
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#endif
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anv_batch_emit(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
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topo.PrimitiveTopologyType = _3DPRIM_POINTLIST;
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}
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anv_batch_emit(batch, GENX(3DSTATE_VF_STATISTICS), vf) {
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vf.StatisticsEnable = false;
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}
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}
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static void
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emit_so_memcpy(struct anv_batch *batch, struct anv_device *device,
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struct anv_address dst, struct anv_address src,
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uint32_t size)
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{
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/* The maximum copy block size is 4 32-bit components at a time. */
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assert(size % 4 == 0);
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unsigned bs = gcd_pow2_u64(16, size);
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enum isl_format format;
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switch (bs) {
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case 4: format = ISL_FORMAT_R32_UINT; break;
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case 8: format = ISL_FORMAT_R32G32_UINT; break;
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case 16: format = ISL_FORMAT_R32G32B32A32_UINT; break;
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default:
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unreachable("Invalid size");
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}
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uint32_t *dw;
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dw = anv_batch_emitn(batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
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GENX(VERTEX_BUFFER_STATE_pack)(batch, dw + 1,
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&(struct GENX(VERTEX_BUFFER_STATE)) {
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.VertexBufferIndex = 32, /* Reserved for this */
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.AddressModifyEnable = true,
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.BufferStartingAddress = src,
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.BufferPitch = bs,
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.MOCS = anv_mocs(device, src.bo, 0),
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#if GFX_VER >= 12
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.L3BypassDisable = true,
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#endif
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.BufferSize = size,
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});
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dw = anv_batch_emitn(batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
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GENX(VERTEX_ELEMENT_STATE_pack)(batch, dw + 1,
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&(struct GENX(VERTEX_ELEMENT_STATE)) {
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.VertexBufferIndex = 32,
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.Valid = true,
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.SourceElementFormat = format,
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.SourceElementOffset = 0,
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.Component0Control = (bs >= 4) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component1Control = (bs >= 8) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component2Control = (bs >= 12) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component3Control = (bs >= 16) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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});
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/* Wa_16011411144:
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*
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* SW must insert a PIPE_CONTROL cmd before and after the
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* 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_*
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* state is not combined with other state changes.
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*/
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if (intel_needs_workaround(device->info, 16011411144))
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genx_batch_emit_pipe_control(batch, device->info, _3D, ANV_PIPE_CS_STALL_BIT);
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anv_batch_emit(batch, GENX(3DSTATE_SO_BUFFER), sob) {
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#if GFX_VER < 12
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sob.SOBufferIndex = 0;
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#else
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sob._3DCommandOpcode = 0;
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sob._3DCommandSubOpcode = SO_BUFFER_INDEX_0_CMD;
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#endif
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sob.MOCS = anv_mocs(device, dst.bo, ISL_SURF_USAGE_STREAM_OUT_BIT),
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sob.SurfaceBaseAddress = dst;
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sob.SOBufferEnable = true;
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sob.SurfaceSize = size / 4 - 1;
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/* As SOL writes out data, it updates the SO_WRITE_OFFSET registers with
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* the end position of the stream. We need to reset this value to 0 at
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* the beginning of the run or else SOL will start at the offset from
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* the previous draw.
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*/
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sob.StreamOffsetWriteEnable = true;
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sob.StreamOffset = 0;
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}
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/* Wa_16011411144: also CS_STALL after touching SO_BUFFER change */
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if (intel_needs_workaround(device->info, 16011411144))
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genx_batch_emit_pipe_control(batch, device->info, _3D, ANV_PIPE_CS_STALL_BIT);
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dw = anv_batch_emitn(batch, 5, GENX(3DSTATE_SO_DECL_LIST),
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.StreamtoBufferSelects0 = (1 << 0),
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.NumEntries0 = 1);
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GENX(SO_DECL_ENTRY_pack)(batch, dw + 3,
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&(struct GENX(SO_DECL_ENTRY)) {
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.Stream0Decl = {
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.OutputBufferSlot = 0,
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.RegisterIndex = 0,
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.ComponentMask = (1 << (bs / 4)) - 1,
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},
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});
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#if GFX_VERx10 == 125
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/* Wa_14015946265: Send PC with CS stall after SO_DECL. */
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genx_batch_emit_pipe_control(batch, device->info, _3D, ANV_PIPE_CS_STALL_BIT);
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#endif
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anv_batch_emit(batch, GENX(3DSTATE_STREAMOUT), so) {
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so.SOFunctionEnable = true;
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so.RenderingDisable = true;
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so.Stream0VertexReadOffset = 0;
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so.Stream0VertexReadLength = DIV_ROUND_UP(32, 64);
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so.Buffer0SurfacePitch = bs;
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}
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genX(emit_breakpoint)(batch, device, true);
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anv_batch_emit(batch, GENX(3DPRIMITIVE), prim) {
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prim.VertexAccessType = SEQUENTIAL;
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prim.VertexCountPerInstance = size / bs;
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prim.StartVertexLocation = 0;
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prim.InstanceCount = 1;
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prim.StartInstanceLocation = 0;
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prim.BaseVertexLocation = 0;
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}
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genX(batch_emit_post_3dprimitive_was)(batch,
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device,
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_3DPRIM_POINTLIST, size / bs);
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genX(emit_breakpoint)(batch, device, false);
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}
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void
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genX(emit_so_memcpy_init)(struct anv_memcpy_state *state,
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struct anv_device *device,
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struct anv_batch *batch)
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{
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memset(state, 0, sizeof(*state));
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state->batch = batch;
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state->device = device;
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const struct intel_l3_config *cfg = intel_get_default_l3_config(device->info);
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genX(emit_l3_config)(batch, device, cfg);
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genX(emit_pipeline_select)(batch, _3D, device);
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emit_common_so_memcpy(batch, device, cfg);
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}
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void
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genX(emit_so_memcpy_fini)(struct anv_memcpy_state *state)
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{
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genX(emit_apply_pipe_flushes)(state->batch, state->device, _3D,
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ANV_PIPE_END_OF_PIPE_SYNC_BIT,
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NULL);
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}
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void
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genX(emit_so_memcpy_end)(struct anv_memcpy_state *state)
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{
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if (intel_device_info_is_dg2(state->device->info))
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genX(batch_set_preemption)(state->batch, state->device->info, _3D, true);
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anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end);
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if ((state->batch->next - state->batch->start) & 4)
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anv_batch_emit(state->batch, GENX(MI_NOOP), noop);
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}
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void
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genX(emit_so_memcpy)(struct anv_memcpy_state *state,
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struct anv_address dst, struct anv_address src,
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uint32_t size)
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{
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if (GFX_VER == 9 &&
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anv_gfx8_9_vb_cache_range_needs_workaround(&state->vb_bound,
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&state->vb_dirty,
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src, size)) {
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genX(emit_apply_pipe_flushes)(state->batch, state->device, _3D,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_VF_CACHE_INVALIDATE_BIT,
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NULL);
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memset(&state->vb_dirty, 0, sizeof(state->vb_dirty));
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}
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emit_so_memcpy(state->batch, state->device, dst, src, size);
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}
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void
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genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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struct anv_address dst, struct anv_address src,
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uint32_t size)
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{
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if (size == 0)
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return;
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if (!cmd_buffer->state.current_l3_config) {
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const struct intel_l3_config *cfg =
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intel_get_default_l3_config(cmd_buffer->device->info);
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genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
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}
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#if GFX_VER == 9
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genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, 32, src, size);
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#endif
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/* Wa_14015814527 */
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genX(apply_task_urb_workaround)(cmd_buffer);
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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genX(flush_pipeline_select_3d)(cmd_buffer);
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emit_common_so_memcpy(&cmd_buffer->batch, cmd_buffer->device,
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cmd_buffer->state.current_l3_config);
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emit_so_memcpy(&cmd_buffer->batch, cmd_buffer->device, dst, src, size);
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#if GFX_VER == 9
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genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer, SEQUENTIAL,
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1ull << 32);
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#endif
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/* Flag all the instructions emitted by the memcpy. */
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struct anv_gfx_dynamic_state *hw_state =
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&cmd_buffer->state.gfx.dyn_state;
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_URB);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_STATISTICS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_TOPOLOGY);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VERTEX_INPUT);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS);
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#if GFX_VER >= 11
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS_2);
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#endif
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#if GFX_VER >= 12
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION);
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#endif
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SO_DECL_LIST);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_STREAMOUT);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SAMPLE_MASK);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MULTISAMPLE);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SF);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SBE);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_HS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TE);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_GS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS);
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if (cmd_buffer->device->vk.enabled_extensions.EXT_mesh_shader) {
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MESH_CONTROL);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TASK_CONTROL);
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}
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cmd_buffer->state.gfx.dirty |= ~(ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER);
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}
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