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c31b4420e7
We scalarize IO to enable further optimizations, such as propagating constant components across shaders, eliminating dead components, and so on. This patch attempts to re-vectorize those operations after the varying optimizations are done. Intel GPUs are a scalar architecture, but IO operations work on whole vec4's at a time, so we'd prefer to have a single IO load per vector rather than 4 scalar IO loads. This re-vectorization can help a lot. Broadcom GPUs, however, really do want scalar IO. radeonsi may want this, or may want to leave it to LLVM. So, we make a new flag in the NIR compiler options struct, and key it off of that, allowing drivers to pick. (It's a bit awkward because we have per-stage settings, but this is about IO between two stages...but I expect drivers to globally prefer one way or the other. We can adjust later if needed.) Reviewed-by: Marek Olšák <marek.olsak@amd.com> |
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| amd | ||
| broadcom | ||
| compiler | ||
| egl | ||
| freedreno | ||
| gallium | ||
| gbm | ||
| getopt | ||
| glx | ||
| gtest | ||
| hgl | ||
| imgui | ||
| intel | ||
| loader | ||
| mapi | ||
| mesa | ||
| util | ||
| vulkan | ||
| meson.build | ||
| SConscript | ||