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feadf303b9
ANGLE is a massive pain to debug because it threads like mad. This at least ensures the shaders aren't weirdly interleaved from multiple threads. Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39244>
337 lines
11 KiB
C
337 lines
11 KiB
C
/*
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* Copyright (C) 2025 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include "pan_compiler.h"
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#include "pan_nir.h"
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#include "bifrost/bifrost_compile.h"
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#include "bifrost/bifrost/disassemble.h"
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#include "bifrost/valhall/disassemble.h"
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#include "midgard/disassemble.h"
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#include "midgard/midgard_compile.h"
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#include "panfrost/model/pan_model.h"
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bool
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pan_will_dump_shaders(unsigned arch)
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{
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if (arch >= 6)
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return bifrost_will_dump_shaders();
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else
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return midgard_will_dump_shaders();
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}
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const nir_shader_compiler_options *
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pan_get_nir_shader_compiler_options(unsigned arch)
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{
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switch (arch) {
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case 4:
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case 5:
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return &midgard_nir_options;
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case 6:
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case 7:
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return &bifrost_nir_options_v6;
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case 9:
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case 10:
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return &bifrost_nir_options_v9;
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case 11:
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case 12:
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case 13:
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return &bifrost_nir_options_v11;
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default:
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assert(!"Unsupported arch");
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return NULL;
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}
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}
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void
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pan_preprocess_nir(nir_shader *nir, unsigned gpu_id)
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{
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if (pan_arch(gpu_id) >= 6)
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bifrost_preprocess_nir(nir, gpu_id);
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else
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midgard_preprocess_nir(nir, gpu_id);
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}
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void
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pan_optimize_nir(nir_shader *nir, unsigned gpu_id)
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{
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assert(pan_arch(gpu_id) >= 6);
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bifrost_optimize_nir(nir, gpu_id);
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}
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void
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pan_postprocess_nir(nir_shader *nir, unsigned gpu_id)
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{
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if (pan_arch(gpu_id) >= 6)
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bifrost_postprocess_nir(nir, gpu_id);
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else
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midgard_postprocess_nir(nir, gpu_id);
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}
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void
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pan_nir_lower_texture_early(nir_shader *nir, unsigned gpu_id)
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{
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nir_lower_tex_options lower_tex_options = {
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.lower_txs_lod = true,
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.lower_txp = ~0,
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.lower_tg4_offsets = true,
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.lower_tg4_broadcom_swizzle = true,
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.lower_txd = pan_arch(gpu_id) < 6,
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.lower_txd_cube_map = true,
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.lower_invalid_implicit_lod = true,
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.lower_index_to_offset = pan_arch(gpu_id) >= 6,
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};
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NIR_PASS(_, nir, nir_lower_tex, &lower_tex_options);
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}
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void
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pan_nir_lower_texture_late(nir_shader *nir, unsigned gpu_id)
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{
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/* This must be called after any lowering of resource indices
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* (panfrost_nir_lower_res_indices / panvk_per_arch(nir_lower_descriptors))
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*/
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if (pan_arch(gpu_id) >= 6)
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bifrost_lower_texture_late_nir(nir, gpu_id);
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}
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/** Converts a per-component mask to a byte mask */
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uint16_t
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pan_to_bytemask(unsigned bytes, unsigned mask)
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{
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switch (bytes) {
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case 0:
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assert(mask == 0);
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return 0;
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case 8:
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return mask;
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case 16: {
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unsigned space =
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(mask & 0x1) | ((mask & 0x2) << (2 - 1)) | ((mask & 0x4) << (4 - 2)) |
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((mask & 0x8) << (6 - 3)) | ((mask & 0x10) << (8 - 4)) |
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((mask & 0x20) << (10 - 5)) | ((mask & 0x40) << (12 - 6)) |
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((mask & 0x80) << (14 - 7));
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return space | (space << 1);
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}
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case 32: {
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unsigned space = (mask & 0x1) | ((mask & 0x2) << (4 - 1)) |
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((mask & 0x4) << (8 - 2)) | ((mask & 0x8) << (12 - 3));
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return space | (space << 1) | (space << 2) | (space << 3);
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}
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case 64: {
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unsigned A = (mask & 0x1) ? 0xFF : 0x00;
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unsigned B = (mask & 0x2) ? 0xFF : 0x00;
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return A | (B << 8);
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}
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default:
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UNREACHABLE("Invalid register mode");
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}
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}
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/* Could optimize with a better data structure if anyone cares, TODO: profile */
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unsigned
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pan_lookup_pushed_ubo(struct pan_ubo_push *push, unsigned ubo, unsigned offs)
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{
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struct pan_ubo_word word = {.ubo = ubo, .offset = offs};
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for (unsigned i = 0; i < push->count; ++i) {
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if (memcmp(push->words + i, &word, sizeof(word)) == 0)
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return i;
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}
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UNREACHABLE("UBO not pushed");
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}
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void
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pan_shader_update_info(struct pan_shader_info *info, nir_shader *s,
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const struct pan_compile_inputs *inputs)
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{
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unsigned arch = pan_arch(inputs->gpu_id);
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info->stage = s->info.stage;
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info->contains_barrier =
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s->info.uses_memory_barrier || s->info.uses_control_barrier;
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info->separable = s->info.separate_shader;
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switch (info->stage) {
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case MESA_SHADER_VERTEX:
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info->attributes_read = s->info.inputs_read;
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info->attributes_read_count = util_bitcount64(info->attributes_read);
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info->attribute_count = info->attributes_read_count;
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if (arch <= 5) {
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if (info->midgard.vs.reads_raw_vertex_id)
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info->attribute_count =
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MAX2(info->attribute_count, PAN_VERTEX_ID + 1);
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bool instance_id =
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BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
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if (instance_id)
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info->attribute_count =
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MAX2(info->attribute_count, PAN_INSTANCE_ID + 1);
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}
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info->vs.writes_point_size =
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s->info.outputs_written & VARYING_BIT_PSIZ;
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info->vs.needs_extended_fifo = arch >= 9 &&
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valhal_writes_extended_fifo(s->info.outputs_written,
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true, inputs->view_mask != 0);
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if (arch >= 9) {
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info->varyings.output_count =
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util_last_bit(s->info.outputs_written >> VARYING_SLOT_VAR0);
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/* Store the mask of special varyings, in case we need to emit ADs
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* later. */
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info->varyings.fixed_varyings =
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pan_get_fixed_varying_mask(s->info.outputs_written);
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}
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break;
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case MESA_SHADER_FRAGMENT:
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if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
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info->fs.writes_depth = true;
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if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
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info->fs.writes_stencil = true;
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if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK))
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info->fs.writes_coverage = true;
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info->fs.outputs_read = s->info.outputs_read;
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info->fs.sample_shading = s->info.fs.uses_sample_shading;
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info->fs.untyped_color_outputs = s->info.fs.untyped_color_outputs;
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info->fs.can_discard = s->info.fs.uses_discard;
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info->fs.early_fragment_tests = s->info.fs.early_fragment_tests;
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/* List of reasons we need to execute frag shaders when things
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* are masked off */
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info->fs.sidefx = s->info.writes_memory || s->info.fs.uses_discard;
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/* With suitable ZSA/blend, is early-z possible? */
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info->fs.can_early_z = !info->fs.sidefx && !info->fs.writes_depth &&
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!info->fs.writes_stencil &&
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!info->fs.writes_coverage;
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/* Similiarly with suitable state, is FPK possible? */
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info->fs.can_fpk = !info->fs.writes_depth && !info->fs.writes_stencil &&
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!info->fs.writes_coverage && !info->fs.can_discard &&
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!info->fs.outputs_read;
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/* Requires the same hardware guarantees, so grouped as one bit
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* in the hardware.
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*/
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info->contains_barrier |= s->info.fs.needs_coarse_quad_helper_invocations;
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info->fs.reads_frag_coord =
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(s->info.inputs_read & VARYING_BIT_POS) ||
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BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRAG_COORD);
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info->fs.reads_primitive_id =
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(s->info.inputs_read & VARYING_BIT_PRIMITIVE_ID) ||
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BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
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info->fs.reads_point_coord =
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s->info.inputs_read & VARYING_BIT_PNTC;
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info->fs.reads_face =
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(s->info.inputs_read & VARYING_BIT_FACE) ||
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BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
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if (arch >= 9) {
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info->varyings.input_count =
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util_last_bit(s->info.inputs_read >> VARYING_SLOT_VAR0);
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/* Store the mask of special varyings, in case we need to emit ADs
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* later. */
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info->varyings.fixed_varyings =
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pan_get_fixed_varying_mask(s->info.inputs_read);
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}
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break;
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default:
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/* Everything else treated as compute */
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info->wls_size = s->info.shared_size;
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break;
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}
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info->outputs_written = s->info.outputs_written;
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info->attribute_count += BITSET_LAST_BIT(s->info.images_used);
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info->writes_global = s->info.writes_memory;
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info->ubo_count = s->info.num_ubos;
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info->sampler_count = info->texture_count =
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BITSET_LAST_BIT(s->info.textures_used);
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unsigned execution_mode = s->info.float_controls_execution_mode;
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info->ftz_fp16 = nir_is_denorm_flush_to_zero(execution_mode, 16);
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info->ftz_fp32 = nir_is_denorm_flush_to_zero(execution_mode, 32);
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if (arch >= 9) {
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/* Valhall hardware doesn't have a "flush FP16, preserve FP32" mode, and
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* we don't advertise independent FP16/FP32 denorm modes in panvk, but
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* it's still possible to have shaders that don't specify any denorm mode
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* for FP32. In that case, default to flush FP32. */
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if (info->ftz_fp16 && !info->ftz_fp32) {
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assert(!nir_is_denorm_preserve(execution_mode, 32));
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info->ftz_fp32 = true;
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}
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}
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}
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void
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pan_shader_compile(nir_shader *s, struct pan_compile_inputs *inputs,
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struct util_dynarray *binary, struct pan_shader_info *info)
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{
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unsigned arch = pan_arch(inputs->gpu_id);
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memset(info, 0, sizeof(*info));
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NIR_PASS(_, s, nir_inline_sysval, nir_intrinsic_load_printf_buffer_size,
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PAN_PRINTF_BUFFER_SIZE - 8);
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if (arch >= 6) {
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bifrost_compile_shader_nir(s, inputs, binary, info);
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/* pan_shader_update_info done in the compile */
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} else {
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midgard_compile_shader_nir(s, inputs, binary, info);
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pan_shader_update_info(info, s, inputs);
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}
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}
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void
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pan_disassemble(FILE *fp, const void *code, size_t size,
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unsigned gpu_id, bool verbose)
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{
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if (pan_arch(gpu_id) >= 9)
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disassemble_valhall(fp, (const uint64_t *)code, size, verbose);
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else if (pan_arch(gpu_id) >= 6)
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disassemble_bifrost(fp, code, size, verbose);
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else
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disassemble_midgard(fp, code, size, gpu_id, verbose);
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}
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