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bfb6c41b64
Reported by clang tools. See: https://clangd.llvm.org/guides/include-cleaner struct ac_cmdbuf had to be moved to ac_cmdbuf_base.h because we can't include ac_cmdbuf.h->sid.h->amdgfxregs.h in radeon_winsys.h for r300. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41091>
128 lines
4 KiB
C
128 lines
4 KiB
C
/*
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* Copyright © 2021 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef AC_SURFACE_TEST_COMMON_H
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#define AC_SURFACE_TEST_COMMON_H
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#include "ac_gpu_info.h"
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#include "amdgfxregs.h"
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#include "amdgpu_devices.h"
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#include "ac_linux_drm.h"
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struct ac_surface_fake_device {
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const char *name;
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const char *device_name;
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int banks_or_pkrs;
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int pipes;
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int se;
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int rb_per_se;
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};
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static struct ac_surface_fake_device ac_surface_fake_devices[] = {
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{"polaris12", "polaris12"},
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{"vega10", "vega10", 4, 2, 2, 2},
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{"vega10_diff_bank", "vega10", 3, 2, 2, 2},
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{"vega10_diff_rb", "vega10", 4, 2, 2, 0},
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{"vega10_diff_pipe", "vega10", 4, 0, 2, 2},
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{"vega10_diff_se", "vega10", 4, 2, 1, 2},
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{"vega20", "vega20", 4, 2, 2, 2},
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{"raven", "raven", 0, 2, 0, 1},
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{"raven2", "raven2", 3, 1, 0, 1},
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/* Just test a bunch of different numbers. (packers, pipes) */
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{"navi10", "navi10", 0, 4},
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{"navi10_diff_pipe", "navi10", 0, 3},
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{"navi10_diff_pkr", "navi10", 1, 4},
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{"navi21", "navi21", 4, 4},
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{"navi21_8pkr", "navi21", 3, 4},
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{"navi22", "navi21", 3, 3},
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{"navi24", "navi21", 2, 2},
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{"vangogh", "vangogh", 1, 2},
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{"vangogh_1pkr", "vangogh", 0, 2},
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{"raphael", "vangogh", 0, 1},
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{"navi31", "navi31", 5, 5},
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{"navi33", "navi33", 3, 3},
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{"phoenix", "phoenix", 2, 2},
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{"phoenix_2pkr", "phoenix", 1, 2},
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{"phoenix2", "phoenix", 0, 2},
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{"phoenix2_2pipe", "phoenix", 0, 1},
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{"gfx12", "gfx1201", 4, 4},
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};
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static const struct amdgpu_device *find_amdgpu_device(const char *name)
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{
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for (int i = 0;i < num_amdgpu_devices; i++) {
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if (strcmp(amdgpu_devices[i].name, name) == 0)
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return &amdgpu_devices[i];
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}
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assert(false);
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return NULL;
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}
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static void get_radeon_info(struct radeon_info *info, const struct ac_surface_fake_device *hw)
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{
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const struct amdgpu_device *dev = find_amdgpu_device(hw->device_name);
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struct amdgpu_gpu_info gpu_info = { 0 };
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/* Emulate ac_drm_read_mm_registers to read relevant fields. */
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gpu_info.gb_addr_cfg = dev->mmr_regs[2];
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if (dev->dev.family < AMDGPU_FAMILY_AI) {
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for (int i = 0; i < 32; i++) {
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for (int j = 0; j < dev->mmr_reg_count; j++) {
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const uint32_t *triple = &dev->mmr_regs[j * 3];
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if (triple[0] == 0x2644 + i)
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gpu_info.gb_tile_mode[i] = triple[2];
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}
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}
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}
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info->kernel_has_modifiers = 1;
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ac_fill_hw_ip_info(info, &dev->dev, AMD_IP_GFX, &dev->hw_ip_gfx);
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ac_fill_hw_ip_info(info, &dev->dev, AMD_IP_COMPUTE, &dev->hw_ip_compute);
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ac_identify_chip(info, &dev->dev);
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ac_fill_memory_info(info, &dev->dev, &dev->mem);
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ac_fill_hw_info(info, &dev->dev);
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ac_fill_tiling_info(info, &gpu_info);
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ac_fill_feature_info(info, &dev->dev);
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ac_fill_bug_info(info);
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ac_fill_tess_info(info);
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ac_fill_compiler_info(info, &dev->dev);
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switch(info->gfx_level) {
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case GFX9:
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info->gb_addr_config = (info->gb_addr_config &
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C_0098F8_NUM_PIPES &
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C_0098F8_NUM_BANKS &
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C_0098F8_NUM_SHADER_ENGINES_GFX9 &
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C_0098F8_NUM_RB_PER_SE) |
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S_0098F8_NUM_PIPES(hw->pipes) |
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S_0098F8_NUM_BANKS(hw->banks_or_pkrs) |
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S_0098F8_NUM_SHADER_ENGINES_GFX9(hw->se) |
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S_0098F8_NUM_RB_PER_SE(hw->rb_per_se);
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break;
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case GFX10:
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case GFX10_3:
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case GFX11:
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case GFX12:
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info->gb_addr_config = (info->gb_addr_config &
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C_0098F8_NUM_PIPES &
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C_0098F8_NUM_PKRS) |
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S_0098F8_NUM_PIPES(hw->pipes) |
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S_0098F8_NUM_PKRS(hw->banks_or_pkrs);
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/* 1 packer implies 1 RB except gfx10 where the field is ignored. */
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info->max_render_backends = info->gfx_level == GFX10 || hw->banks_or_pkrs ? 2 : 1;
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break;
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default:
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break;
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}
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}
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#endif
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