Samuel Pitoiset bf6c8ee864 radv: try to keep HTILE compressed for READ_ONLY_OPTIMAL layout ... It should be handled like DEPTH_STENCIL_READ_ONLY_OPTIMAL. This fixes an issue with VRS attachment because HTILE was considered disabled for READ_ONLY_OPTIMAL but there is no reasons to disable it as long as the image is only used as a depth/stencil attachment. Otherwise, when HTILE is disabled, VRS rates are ignored. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8675 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22468> (cherry picked from commit f11a4a09b0)		2023-04-16 22:37:09 +01:00
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addrlib	amd: update addrlib	2023-03-29 20:36:09 +00:00
ci	radv: fix detecting FMASK_DECOMPRESS/DCC_DECOMPRESS meta pipelines	2023-04-16 22:16:17 +01:00
common	ac,aco: move gfx10 ngg prim count zero workaround to nir	2023-04-13 08:12:03 +00:00
compiler	ac,aco: move gfx10 ngg prim count zero workaround to nir	2023-04-13 08:12:03 +00:00
drm-shim	r300: use drm_shim_override	2022-11-16 14:37:47 +00:00
llvm	ac,aco: move gfx10 ngg prim count zero workaround to nir	2023-04-13 08:12:03 +00:00
registers	amd/registers: use gfx9 packet definitions for gfx940	2023-04-06 15:00:54 +00:00
vulkan	radv: try to keep HTILE compressed for READ_ONLY_OPTIMAL layout	2023-04-16 22:37:09 +01:00
.clang-format	amd: Add radv_foreach_stage to ForEachMacros.	2023-03-27 08:29:35 +00:00
meson.build	meson: build radeon drm-shim also for r300 and r600	2022-11-16 14:37:47 +00:00