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3c867bf2c7
This gathers a number of sources into a contiguous vector register. Eventually, the plan is that it will use a MOV for a single source, or LOAD_PAYLOAD for multiple sources. For now, it emits a series of MOVs to allow us to rewrite a bunch of existing code to use the new helper, then change them all over at once later. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
920 lines
30 KiB
C++
920 lines
30 KiB
C++
/* -*- c++ -*- */
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/*
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* Copyright © 2010-2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef BRW_FS_BUILDER_H
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#define BRW_FS_BUILDER_H
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#include "brw_ir_fs.h"
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#include "brw_eu.h"
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#include "brw_fs.h"
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namespace brw {
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/**
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* Toolbox to assemble an FS IR program out of individual instructions.
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*/
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class fs_builder {
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public:
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/**
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* Construct an fs_builder that inserts instructions into \p shader.
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* \p dispatch_width gives the native execution width of the program.
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*/
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fs_builder(fs_visitor *shader,
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unsigned dispatch_width) :
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shader(shader), block(NULL), cursor(NULL),
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_dispatch_width(dispatch_width),
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_group(0),
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force_writemask_all(false),
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annotation()
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{
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}
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explicit fs_builder(fs_visitor *s) : fs_builder(s, s->dispatch_width) {}
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/**
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* Construct an fs_builder that inserts instructions into \p shader
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* before instruction \p inst in basic block \p block. The default
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* execution controls and debug annotation are initialized from the
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* instruction passed as argument.
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*/
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fs_builder(fs_visitor *shader, bblock_t *block, fs_inst *inst) :
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shader(shader), block(block), cursor(inst),
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_dispatch_width(inst->exec_size),
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_group(inst->group),
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force_writemask_all(inst->force_writemask_all)
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{
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annotation.str = inst->annotation;
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annotation.ir = inst->ir;
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}
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/**
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* Construct an fs_builder that inserts instructions before \p cursor in
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* basic block \p block, inheriting other code generation parameters
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* from this.
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*/
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fs_builder
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at(bblock_t *block, exec_node *cursor) const
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{
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fs_builder bld = *this;
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bld.block = block;
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bld.cursor = cursor;
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return bld;
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}
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/**
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* Construct an fs_builder appending instructions at the end of the
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* instruction list of the shader, inheriting other code generation
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* parameters from this.
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*/
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fs_builder
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at_end() const
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{
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return at(NULL, (exec_node *)&shader->instructions.tail_sentinel);
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}
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/**
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* Construct a builder specifying the default SIMD width and group of
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* channel enable signals, inheriting other code generation parameters
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* from this.
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*
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* \p n gives the default SIMD width, \p i gives the slot group used for
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* predication and control flow masking in multiples of \p n channels.
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*/
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fs_builder
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group(unsigned n, unsigned i) const
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{
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fs_builder bld = *this;
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if (n <= dispatch_width() && i < dispatch_width() / n) {
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bld._group += i * n;
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} else {
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/* The requested channel group isn't a subset of the channel group
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* of this builder, which means that the resulting instructions
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* would use (potentially undefined) channel enable signals not
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* specified by the parent builder. That's only valid if the
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* instruction doesn't have per-channel semantics, in which case
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* we should clear off the default group index in order to prevent
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* emitting instructions with channel group not aligned to their
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* own execution size.
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*/
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assert(force_writemask_all);
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bld._group = 0;
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}
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bld._dispatch_width = n;
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return bld;
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}
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/**
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* Alias for group() with width equal to eight.
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*/
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fs_builder
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quarter(unsigned i) const
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{
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return group(8, i);
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}
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/**
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* Construct a builder with per-channel control flow execution masking
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* disabled if \p b is true. If control flow execution masking is
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* already disabled this has no effect.
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*/
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fs_builder
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exec_all(bool b = true) const
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{
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fs_builder bld = *this;
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if (b)
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bld.force_writemask_all = true;
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return bld;
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}
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/**
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* Construct a builder with the given debug annotation info.
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*/
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fs_builder
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annotate(const char *str, const void *ir = NULL) const
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{
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fs_builder bld = *this;
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bld.annotation.str = str;
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bld.annotation.ir = ir;
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return bld;
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}
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/**
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* Get the SIMD width in use.
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*/
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unsigned
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dispatch_width() const
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{
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return _dispatch_width;
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}
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/**
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* Get the channel group in use.
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*/
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unsigned
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group() const
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{
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return _group;
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}
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/**
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* Allocate a virtual register of natural vector size (one for this IR)
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* and SIMD width. \p n gives the amount of space to allocate in
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* dispatch_width units (which is just enough space for one logical
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* component in this IR).
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*/
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fs_reg
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vgrf(enum brw_reg_type type, unsigned n = 1) const
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{
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const unsigned unit = reg_unit(shader->devinfo);
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assert(dispatch_width() <= 32);
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if (n > 0)
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return fs_reg(VGRF, shader->alloc.allocate(
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DIV_ROUND_UP(n * brw_type_size_bytes(type) * dispatch_width(),
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unit * REG_SIZE) * unit),
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type);
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else
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return retype(null_reg_ud(), type);
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}
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/**
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* Create a null register of floating type.
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*/
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fs_reg
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null_reg_f() const
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{
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return fs_reg(retype(brw_null_reg(), BRW_TYPE_F));
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}
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fs_reg
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null_reg_df() const
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{
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return fs_reg(retype(brw_null_reg(), BRW_TYPE_DF));
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}
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/**
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* Create a null register of signed integer type.
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*/
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fs_reg
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null_reg_d() const
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{
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return fs_reg(retype(brw_null_reg(), BRW_TYPE_D));
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}
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/**
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* Create a null register of unsigned integer type.
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*/
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fs_reg
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null_reg_ud() const
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{
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return fs_reg(retype(brw_null_reg(), BRW_TYPE_UD));
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}
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/**
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* Insert an instruction into the program.
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*/
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fs_inst *
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emit(const fs_inst &inst) const
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{
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return emit(new(shader->mem_ctx) fs_inst(inst));
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}
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/**
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* Create and insert a nullary control instruction into the program.
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*/
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fs_inst *
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emit(enum opcode opcode) const
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{
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return emit(fs_inst(opcode, dispatch_width()));
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}
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/**
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* Create and insert a nullary instruction into the program.
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*/
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fs_inst *
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emit(enum opcode opcode, const fs_reg &dst) const
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{
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return emit(fs_inst(opcode, dispatch_width(), dst));
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}
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/**
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* Create and insert a unary instruction into the program.
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*/
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fs_inst *
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emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0) const
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{
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return emit(fs_inst(opcode, dispatch_width(), dst, src0));
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}
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/**
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* Create and insert a binary instruction into the program.
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*/
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fs_inst *
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emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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const fs_reg &src1) const
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{
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return emit(fs_inst(opcode, dispatch_width(), dst,
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src0, src1));
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}
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/**
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* Create and insert a ternary instruction into the program.
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*/
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fs_inst *
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emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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const fs_reg &src1, const fs_reg &src2) const
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{
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switch (opcode) {
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case BRW_OPCODE_BFE:
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case BRW_OPCODE_BFI2:
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case BRW_OPCODE_MAD:
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case BRW_OPCODE_LRP:
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return emit(fs_inst(opcode, dispatch_width(), dst,
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fix_3src_operand(src0),
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fix_3src_operand(src1),
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fix_3src_operand(src2)));
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default:
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return emit(fs_inst(opcode, dispatch_width(), dst,
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src0, src1, src2));
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}
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}
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/**
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* Create and insert an instruction with a variable number of sources
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* into the program.
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*/
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fs_inst *
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emit(enum opcode opcode, const fs_reg &dst, const fs_reg srcs[],
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unsigned n) const
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{
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/* Use the emit() methods for specific operand counts to ensure that
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* opcode-specific operand fixups occur.
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*/
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if (n == 2) {
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return emit(opcode, dst, srcs[0], srcs[1]);
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} else if (n == 3) {
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return emit(opcode, dst, srcs[0], srcs[1], srcs[2]);
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} else {
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return emit(fs_inst(opcode, dispatch_width(), dst, srcs, n));
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}
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}
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/**
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* Insert a preallocated instruction into the program.
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*/
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fs_inst *
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emit(fs_inst *inst) const
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{
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assert(inst->exec_size <= 32);
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assert(inst->exec_size == dispatch_width() ||
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force_writemask_all);
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inst->group = _group;
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inst->force_writemask_all = force_writemask_all;
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inst->annotation = annotation.str;
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inst->ir = annotation.ir;
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if (block)
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static_cast<fs_inst *>(cursor)->insert_before(block, inst);
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else
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cursor->insert_before(inst);
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return inst;
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}
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/**
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* Select \p src0 if the comparison of both sources with the given
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* conditional mod evaluates to true, otherwise select \p src1.
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*
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* Generally useful to get the minimum or maximum of two values.
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*/
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fs_inst *
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emit_minmax(const fs_reg &dst, const fs_reg &src0,
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const fs_reg &src1, brw_conditional_mod mod) const
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{
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assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L);
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/* In some cases we can't have bytes as operand for src1, so use the
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* same type for both operand.
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*/
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return set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
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fix_unsigned_negate(src1)));
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}
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/**
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* Copy any live channel from \p src to the first channel of the result.
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*/
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fs_reg
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emit_uniformize(const fs_reg &src) const
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{
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/* FIXME: We use a vector chan_index and dst to allow constant and
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* copy propagration to move result all the way into the consuming
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* instruction (typically a surface index or sampler index for a
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* send). This uses 1 or 3 extra hw registers in 16 or 32 wide
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* dispatch. Once we teach const/copy propagation about scalars we
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* should go back to scalar destinations here.
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*/
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const fs_builder ubld = exec_all();
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const fs_reg chan_index = vgrf(BRW_TYPE_UD);
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const fs_reg dst = vgrf(src.type);
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ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index);
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ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0));
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return fs_reg(component(dst, 0));
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}
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fs_reg
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move_to_vgrf(const fs_reg &src, unsigned num_components) const
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{
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fs_reg *const src_comps = new fs_reg[num_components];
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for (unsigned i = 0; i < num_components; i++)
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src_comps[i] = offset(src, dispatch_width(), i);
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const fs_reg dst = vgrf(src.type, num_components);
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LOAD_PAYLOAD(dst, src_comps, num_components, 0);
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delete[] src_comps;
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return fs_reg(dst);
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}
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void
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emit_scan_step(enum opcode opcode, brw_conditional_mod mod,
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const fs_reg &tmp,
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unsigned left_offset, unsigned left_stride,
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unsigned right_offset, unsigned right_stride) const
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{
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fs_reg left, right;
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left = horiz_stride(horiz_offset(tmp, left_offset), left_stride);
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right = horiz_stride(horiz_offset(tmp, right_offset), right_stride);
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if ((tmp.type == BRW_TYPE_Q || tmp.type == BRW_TYPE_UQ) &&
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!shader->devinfo->has_64bit_int) {
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switch (opcode) {
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case BRW_OPCODE_MUL:
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/* This will get lowered by integer MUL lowering */
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set_condmod(mod, emit(opcode, right, left, right));
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break;
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case BRW_OPCODE_SEL: {
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/* In order for the comparisons to work out right, we need our
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* comparisons to be strict.
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*/
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assert(mod == BRW_CONDITIONAL_L || mod == BRW_CONDITIONAL_GE);
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if (mod == BRW_CONDITIONAL_GE)
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mod = BRW_CONDITIONAL_G;
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/* We treat the bottom 32 bits as unsigned regardless of
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* whether or not the integer as a whole is signed.
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*/
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fs_reg right_low = subscript(right, BRW_TYPE_UD, 0);
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fs_reg left_low = subscript(left, BRW_TYPE_UD, 0);
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/* The upper bits get the same sign as the 64-bit type */
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brw_reg_type type32 = brw_type_with_size(tmp.type, 32);
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fs_reg right_high = subscript(right, type32, 1);
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fs_reg left_high = subscript(left, type32, 1);
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/* Build up our comparison:
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*
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* l_hi < r_hi || (l_hi == r_hi && l_low < r_low)
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*/
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CMP(null_reg_ud(), retype(left_low, BRW_TYPE_UD),
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retype(right_low, BRW_TYPE_UD), mod);
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set_predicate(BRW_PREDICATE_NORMAL,
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CMP(null_reg_ud(), left_high, right_high,
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BRW_CONDITIONAL_EQ));
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set_predicate_inv(BRW_PREDICATE_NORMAL, true,
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CMP(null_reg_ud(), left_high, right_high, mod));
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/* We could use selects here or we could use predicated MOVs
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* because the destination and second source (if it were a SEL)
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* are the same.
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*/
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set_predicate(BRW_PREDICATE_NORMAL, MOV(right_low, left_low));
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set_predicate(BRW_PREDICATE_NORMAL, MOV(right_high, left_high));
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break;
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}
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default:
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unreachable("Unsupported 64-bit scan op");
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}
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} else {
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set_condmod(mod, emit(opcode, right, left, right));
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}
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}
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void
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emit_scan(enum opcode opcode, const fs_reg &tmp,
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unsigned cluster_size, brw_conditional_mod mod) const
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{
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assert(dispatch_width() >= 8);
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/* The instruction splitting code isn't advanced enough to split
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* these so we need to handle that ourselves.
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*/
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if (dispatch_width() * brw_type_size_bytes(tmp.type) > 2 * REG_SIZE) {
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const unsigned half_width = dispatch_width() / 2;
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const fs_builder ubld = exec_all().group(half_width, 0);
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fs_reg left = tmp;
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fs_reg right = horiz_offset(tmp, half_width);
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ubld.emit_scan(opcode, left, cluster_size, mod);
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ubld.emit_scan(opcode, right, cluster_size, mod);
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if (cluster_size > half_width) {
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ubld.emit_scan_step(opcode, mod, tmp,
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half_width - 1, 0, half_width, 1);
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}
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return;
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}
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if (cluster_size > 1) {
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const fs_builder ubld = exec_all().group(dispatch_width() / 2, 0);
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ubld.emit_scan_step(opcode, mod, tmp, 0, 2, 1, 2);
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}
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if (cluster_size > 2) {
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if (brw_type_size_bytes(tmp.type) <= 4) {
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const fs_builder ubld =
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exec_all().group(dispatch_width() / 4, 0);
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ubld.emit_scan_step(opcode, mod, tmp, 1, 4, 2, 4);
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ubld.emit_scan_step(opcode, mod, tmp, 1, 4, 3, 4);
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} else {
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/* For 64-bit types, we have to do things differently because
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* the code above would land us with destination strides that
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* the hardware can't handle. Fortunately, we'll only be
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* 8-wide in that case and it's the same number of
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* instructions.
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*/
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const fs_builder ubld = exec_all().group(2, 0);
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for (unsigned i = 0; i < dispatch_width(); i += 4)
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ubld.emit_scan_step(opcode, mod, tmp, i + 1, 0, i + 2, 1);
|
|
}
|
|
}
|
|
|
|
for (unsigned i = 4;
|
|
i < MIN2(cluster_size, dispatch_width());
|
|
i *= 2) {
|
|
const fs_builder ubld = exec_all().group(i, 0);
|
|
ubld.emit_scan_step(opcode, mod, tmp, i - 1, 0, i, 1);
|
|
|
|
if (dispatch_width() > i * 2)
|
|
ubld.emit_scan_step(opcode, mod, tmp, i * 3 - 1, 0, i * 3, 1);
|
|
|
|
if (dispatch_width() > i * 4) {
|
|
ubld.emit_scan_step(opcode, mod, tmp, i * 5 - 1, 0, i * 5, 1);
|
|
ubld.emit_scan_step(opcode, mod, tmp, i * 7 - 1, 0, i * 7, 1);
|
|
}
|
|
}
|
|
}
|
|
|
|
fs_inst *
|
|
emit_undef_for_dst(const fs_inst *old_inst) const
|
|
{
|
|
assert(old_inst->dst.file == VGRF);
|
|
fs_inst *inst = emit(SHADER_OPCODE_UNDEF,
|
|
retype(old_inst->dst, BRW_TYPE_UD));
|
|
inst->size_written = old_inst->size_written;
|
|
|
|
return inst;
|
|
}
|
|
|
|
/**
|
|
* Assorted arithmetic ops.
|
|
* @{
|
|
*/
|
|
#define _ALU1(prefix, op) \
|
|
fs_inst * \
|
|
op(const fs_reg &dst, const fs_reg &src0) const \
|
|
{ \
|
|
assert(_dispatch_width == 1 || \
|
|
(dst.file >= VGRF && dst.stride != 0) || \
|
|
(dst.file < VGRF && dst.hstride != 0)); \
|
|
return emit(prefix##op, dst, src0); \
|
|
} \
|
|
fs_reg \
|
|
op(const fs_reg &src0, fs_inst **out = NULL) const \
|
|
{ \
|
|
fs_inst *inst = op(vgrf(src0.type), src0); \
|
|
if (out) *out = inst; \
|
|
return inst->dst; \
|
|
}
|
|
#define ALU1(op) _ALU1(BRW_OPCODE_, op)
|
|
#define VIRT1(op) _ALU1(SHADER_OPCODE_, op)
|
|
|
|
#define _ALU2(prefix, op) \
|
|
fs_inst * \
|
|
op(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1) const \
|
|
{ \
|
|
return emit(prefix##op, dst, src0, src1); \
|
|
} \
|
|
fs_reg \
|
|
op(const fs_reg &src0, const fs_reg &src1, fs_inst **out = NULL) const \
|
|
{ \
|
|
enum brw_reg_type inferred_dst_type = \
|
|
brw_type_larger_of(src0.type, src1.type); \
|
|
fs_inst *inst = op(vgrf(inferred_dst_type), src0, src1); \
|
|
if (out) *out = inst; \
|
|
return inst->dst; \
|
|
}
|
|
#define ALU2(op) _ALU2(BRW_OPCODE_, op)
|
|
#define VIRT2(op) _ALU2(SHADER_OPCODE_, op)
|
|
|
|
#define ALU2_ACC(op) \
|
|
fs_inst * \
|
|
op(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1) const \
|
|
{ \
|
|
fs_inst *inst = emit(BRW_OPCODE_##op, dst, src0, src1); \
|
|
inst->writes_accumulator = true; \
|
|
return inst; \
|
|
}
|
|
|
|
#define ALU3(op) \
|
|
fs_inst * \
|
|
op(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1, \
|
|
const fs_reg &src2) const \
|
|
{ \
|
|
return emit(BRW_OPCODE_##op, dst, src0, src1, src2); \
|
|
}
|
|
|
|
ALU2(ADD)
|
|
ALU3(ADD3)
|
|
ALU2_ACC(ADDC)
|
|
ALU2(AND)
|
|
ALU2(ASR)
|
|
ALU2(AVG)
|
|
ALU3(BFE)
|
|
ALU2(BFI1)
|
|
ALU3(BFI2)
|
|
ALU1(BFREV)
|
|
ALU1(CBIT)
|
|
ALU2(DP2)
|
|
ALU2(DP3)
|
|
ALU2(DP4)
|
|
ALU2(DPH)
|
|
ALU1(FBH)
|
|
ALU1(FBL)
|
|
ALU1(FRC)
|
|
ALU3(DP4A)
|
|
ALU2(LINE)
|
|
ALU1(LZD)
|
|
ALU2(MAC)
|
|
ALU2_ACC(MACH)
|
|
ALU3(MAD)
|
|
ALU1(MOV)
|
|
ALU2(MUL)
|
|
ALU1(NOT)
|
|
ALU2(OR)
|
|
ALU2(PLN)
|
|
ALU1(RNDD)
|
|
ALU1(RNDE)
|
|
ALU1(RNDU)
|
|
ALU1(RNDZ)
|
|
ALU2(ROL)
|
|
ALU2(ROR)
|
|
ALU2(SAD2)
|
|
ALU2_ACC(SADA2)
|
|
ALU2(SEL)
|
|
ALU2(SHL)
|
|
ALU2(SHR)
|
|
ALU2_ACC(SUBB)
|
|
ALU2(XOR)
|
|
|
|
VIRT1(RCP)
|
|
VIRT1(RSQ)
|
|
VIRT1(SQRT)
|
|
VIRT1(EXP2)
|
|
VIRT1(LOG2)
|
|
VIRT2(POW)
|
|
VIRT2(INT_QUOTIENT)
|
|
VIRT2(INT_REMAINDER)
|
|
VIRT1(SIN)
|
|
VIRT1(COS)
|
|
|
|
#undef ALU3
|
|
#undef ALU2_ACC
|
|
#undef ALU2
|
|
#undef VIRT2
|
|
#undef _ALU2
|
|
#undef ALU1
|
|
#undef VIRT1
|
|
#undef _ALU1
|
|
/** @} */
|
|
|
|
/**
|
|
* CMP: Sets the low bit of the destination channels with the result
|
|
* of the comparison, while the upper bits are undefined, and updates
|
|
* the flag register with the packed 16 bits of the result.
|
|
*/
|
|
fs_inst *
|
|
CMP(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1,
|
|
brw_conditional_mod condition) const
|
|
{
|
|
/* Take the instruction:
|
|
*
|
|
* CMP null<d> src0<f> src1<f>
|
|
*
|
|
* Original gfx4 does type conversion to the destination type
|
|
* before comparison, producing garbage results for floating
|
|
* point comparisons.
|
|
*
|
|
* The destination type doesn't matter on newer generations,
|
|
* so we set the type to match src0 so we can compact the
|
|
* instruction.
|
|
*/
|
|
return set_condmod(condition,
|
|
emit(BRW_OPCODE_CMP, retype(dst, src0.type),
|
|
fix_unsigned_negate(src0),
|
|
fix_unsigned_negate(src1)));
|
|
}
|
|
|
|
/**
|
|
* CMPN: Behaves like CMP, but produces true if src1 is NaN.
|
|
*/
|
|
fs_inst *
|
|
CMPN(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1,
|
|
brw_conditional_mod condition) const
|
|
{
|
|
/* Take the instruction:
|
|
*
|
|
* CMP null<d> src0<f> src1<f>
|
|
*
|
|
* Original gfx4 does type conversion to the destination type
|
|
* before comparison, producing garbage results for floating
|
|
* point comparisons.
|
|
*
|
|
* The destination type doesn't matter on newer generations,
|
|
* so we set the type to match src0 so we can compact the
|
|
* instruction.
|
|
*/
|
|
return set_condmod(condition,
|
|
emit(BRW_OPCODE_CMPN, retype(dst, src0.type),
|
|
fix_unsigned_negate(src0),
|
|
fix_unsigned_negate(src1)));
|
|
}
|
|
|
|
/**
|
|
* Gfx4 predicated IF.
|
|
*/
|
|
fs_inst *
|
|
IF(brw_predicate predicate) const
|
|
{
|
|
return set_predicate(predicate, emit(BRW_OPCODE_IF));
|
|
}
|
|
|
|
/**
|
|
* CSEL: dst = src2 <op> 0.0f ? src0 : src1
|
|
*/
|
|
fs_inst *
|
|
CSEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1,
|
|
const fs_reg &src2, brw_conditional_mod condition) const
|
|
{
|
|
/* CSEL only operates on floats, so we can't do integer </<=/>=/>
|
|
* comparisons. Zero/non-zero (== and !=) comparisons almost work.
|
|
* 0x80000000 fails because it is -0.0, and -0.0 == 0.0.
|
|
*/
|
|
assert(src2.type == BRW_TYPE_F);
|
|
|
|
return set_condmod(condition,
|
|
emit(BRW_OPCODE_CSEL,
|
|
retype(dst, BRW_TYPE_F),
|
|
retype(src0, BRW_TYPE_F),
|
|
retype(src1, BRW_TYPE_F),
|
|
src2));
|
|
}
|
|
|
|
/**
|
|
* Emit a linear interpolation instruction.
|
|
*/
|
|
fs_inst *
|
|
LRP(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
|
|
const fs_reg &a) const
|
|
{
|
|
if (shader->devinfo->ver <= 10) {
|
|
/* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
|
|
* we need to reorder the operands.
|
|
*/
|
|
return emit(BRW_OPCODE_LRP, dst, a, y, x);
|
|
|
|
} else {
|
|
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
|
|
const fs_reg y_times_a = vgrf(dst.type);
|
|
const fs_reg one_minus_a = vgrf(dst.type);
|
|
const fs_reg x_times_one_minus_a = vgrf(dst.type);
|
|
|
|
MUL(y_times_a, y, a);
|
|
ADD(one_minus_a, negate(a), brw_imm_f(1.0f));
|
|
MUL(x_times_one_minus_a, x, fs_reg(one_minus_a));
|
|
return ADD(dst, fs_reg(x_times_one_minus_a), fs_reg(y_times_a));
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Collect a number of registers in a contiguous range of registers.
|
|
*/
|
|
fs_inst *
|
|
LOAD_PAYLOAD(const fs_reg &dst, const fs_reg *src,
|
|
unsigned sources, unsigned header_size) const
|
|
{
|
|
fs_inst *inst = emit(SHADER_OPCODE_LOAD_PAYLOAD, dst, src, sources);
|
|
inst->header_size = header_size;
|
|
inst->size_written = header_size * REG_SIZE;
|
|
for (unsigned i = header_size; i < sources; i++) {
|
|
inst->size_written += dispatch_width() * brw_type_size_bytes(src[i].type) *
|
|
dst.stride;
|
|
}
|
|
|
|
return inst;
|
|
}
|
|
|
|
void
|
|
VEC(const fs_reg &dst, const fs_reg *src, unsigned sources) const
|
|
{
|
|
/* For now, this emits a series of MOVs to ease the transition
|
|
* to the new helper. The intention is to have this emit either
|
|
* a single MOV or a LOAD_PAYLOAD to fully initialize dst from a
|
|
* the list of sources.
|
|
*/
|
|
for (unsigned i = 0; i < sources; i++)
|
|
MOV(offset(dst, dispatch_width(), i), src[i]);
|
|
}
|
|
|
|
fs_inst *
|
|
SYNC(enum tgl_sync_function sync) const
|
|
{
|
|
return emit(BRW_OPCODE_SYNC, null_reg_ud(), brw_imm_ud(sync));
|
|
}
|
|
|
|
fs_inst *
|
|
UNDEF(const fs_reg &dst) const
|
|
{
|
|
assert(dst.file == VGRF);
|
|
assert(dst.offset % REG_SIZE == 0);
|
|
fs_inst *inst = emit(SHADER_OPCODE_UNDEF,
|
|
retype(dst, BRW_TYPE_UD));
|
|
inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE - dst.offset;
|
|
|
|
return inst;
|
|
}
|
|
|
|
fs_inst *
|
|
DPAS(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1, const fs_reg &src2,
|
|
unsigned sdepth, unsigned rcount) const
|
|
{
|
|
assert(_dispatch_width == 8 * reg_unit(shader->devinfo));
|
|
assert(sdepth == 8);
|
|
assert(rcount == 1 || rcount == 2 || rcount == 4 || rcount == 8);
|
|
|
|
fs_inst *inst = emit(BRW_OPCODE_DPAS, dst, src0, src1, src2);
|
|
inst->sdepth = sdepth;
|
|
inst->rcount = rcount;
|
|
|
|
if (dst.type == BRW_TYPE_HF) {
|
|
inst->size_written = rcount * REG_SIZE / 2;
|
|
} else {
|
|
inst->size_written = rcount * REG_SIZE;
|
|
}
|
|
|
|
return inst;
|
|
}
|
|
|
|
fs_visitor *shader;
|
|
|
|
fs_inst *BREAK() { return emit(BRW_OPCODE_BREAK); }
|
|
fs_inst *DO() { return emit(BRW_OPCODE_DO); }
|
|
fs_inst *ENDIF() { return emit(BRW_OPCODE_ENDIF); }
|
|
fs_inst *NOP() { return emit(BRW_OPCODE_NOP); }
|
|
fs_inst *WHILE() { return emit(BRW_OPCODE_WHILE); }
|
|
fs_inst *CONTINUE() { return emit(BRW_OPCODE_CONTINUE); }
|
|
|
|
private:
|
|
/**
|
|
* Workaround for negation of UD registers. See comment in
|
|
* fs_generator::generate_code() for more details.
|
|
*/
|
|
fs_reg
|
|
fix_unsigned_negate(const fs_reg &src) const
|
|
{
|
|
if (src.type == BRW_TYPE_UD &&
|
|
src.negate) {
|
|
fs_reg temp = vgrf(BRW_TYPE_UD);
|
|
MOV(temp, src);
|
|
return fs_reg(temp);
|
|
} else {
|
|
return src;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Workaround for source register modes not supported by the ternary
|
|
* instruction encoding.
|
|
*/
|
|
fs_reg
|
|
fix_3src_operand(const fs_reg &src) const
|
|
{
|
|
switch (src.file) {
|
|
case FIXED_GRF:
|
|
/* FINISHME: Could handle scalar region, other stride=1 regions */
|
|
if (src.vstride != BRW_VERTICAL_STRIDE_8 ||
|
|
src.width != BRW_WIDTH_8 ||
|
|
src.hstride != BRW_HORIZONTAL_STRIDE_1)
|
|
break;
|
|
FALLTHROUGH;
|
|
case ATTR:
|
|
case VGRF:
|
|
case UNIFORM:
|
|
case IMM:
|
|
return src;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
fs_reg expanded = vgrf(src.type);
|
|
MOV(expanded, src);
|
|
return expanded;
|
|
}
|
|
|
|
bblock_t *block;
|
|
exec_node *cursor;
|
|
|
|
unsigned _dispatch_width;
|
|
unsigned _group;
|
|
bool force_writemask_all;
|
|
|
|
/** Debug annotation info. */
|
|
struct {
|
|
const char *str;
|
|
const void *ir;
|
|
} annotation;
|
|
};
|
|
}
|
|
|
|
static inline fs_reg
|
|
offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta)
|
|
{
|
|
return offset(reg, bld.dispatch_width(), delta);
|
|
}
|
|
|
|
#endif
|