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b75f095bc7
Commands used to do the changes: export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965" grep -E "gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+\)/gfx\1/g" Exclude pack.h and xml changes in this patch: grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g" grep -E "gfx[[:digit:]]+\.xml" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+\.xml\)/gen\1/g" Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
68 lines
2.8 KiB
C
68 lines
2.8 KiB
C
/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef IRIS_DEFINES_H
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#define IRIS_DEFINES_H
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/**
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* @file iris_defines.h
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*
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* Random hardware #defines that we're not using GENXML for.
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*/
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#define MI_PREDICATE (0xC << 23)
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# define MI_PREDICATE_LOADOP_KEEP (0 << 6)
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# define MI_PREDICATE_LOADOP_LOAD (2 << 6)
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# define MI_PREDICATE_LOADOP_LOADINV (3 << 6)
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# define MI_PREDICATE_COMBINEOP_SET (0 << 3)
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# define MI_PREDICATE_COMBINEOP_AND (1 << 3)
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# define MI_PREDICATE_COMBINEOP_OR (2 << 3)
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# define MI_PREDICATE_COMBINEOP_XOR (3 << 3)
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# define MI_PREDICATE_COMPAREOP_TRUE (0 << 0)
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# define MI_PREDICATE_COMPAREOP_FALSE (1 << 0)
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# define MI_PREDICATE_COMPAREOP_SRCS_EQUAL (2 << 0)
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# define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL (3 << 0)
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/* Predicate registers */
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#define MI_PREDICATE_SRC0 0x2400
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#define MI_PREDICATE_SRC1 0x2408
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#define MI_PREDICATE_DATA 0x2410
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#define MI_PREDICATE_RESULT 0x2418
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#define MI_PREDICATE_RESULT_1 0x241C
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#define MI_PREDICATE_RESULT_2 0x2214
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#define CS_GPR(n) (0x2600 + (n) * 8)
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/* The number of bits in our TIMESTAMP queries. */
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#define TIMESTAMP_BITS 36
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/* For gfx12 we set the streamout buffers using 4 separate commands
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* (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
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* of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
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* 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
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* 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
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* SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
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* 3DSTATE_SO_BUFFER_INDEX_0.
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*/
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#define SO_BUFFER_INDEX_0_CMD 0x60
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#endif
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