Ian Romanick bac10ef4aa intel/fs: Add DP4A to get_lowered_simd_width ... While working on cooperative matrix support, I noticed some invalid DP4A instructions being generated. dp4a(32) g33<1>UD g21<8,8,1>UD g1.0<0,1,0>UD g9<1,1,1>UD This violates the constraint that the destination or a source can only access two consecutive GRFs. I'm a little surprised that validation didn't catch this. Perhaps because it's a 3 source instruction? Either way, it seems like a bigger project to fix that. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Fixes: 0f809dbf40 ("intel/compiler: Basic support for DP4A instruction") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25554>		2023-10-07 02:27:53 +00:00
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blorp	blorp: fix hangs with mesh enabled	2023-09-12 02:51:31 +00:00
ci	ci: skip dEQP-VK.api.driver_properties.conformance_version for everyone	2023-10-06 17:37:20 +00:00
common	intel/common: Add sse2_args for 32-bit build when -Dsse2=false was set	2023-09-15 17:39:55 -07:00
compiler	intel/fs: Add DP4A to get_lowered_simd_width	2023-10-07 02:27:53 +00:00
dev	intel: Sync xe_drm.h	2023-09-13 16:38:15 +00:00
ds	intel/ds: track acceleration RT commands	2023-10-06 11:10:12 +00:00
genxml	intel/genxml: remove HDC from gen11.xml, it is not available	2023-10-02 12:05:54 +00:00
isl	isl: Use 16-bit instead of 8-bits for surface format info fields	2023-10-02 17:24:33 +00:00
nullhw-layer	meson: support installation tags	2023-09-11 13:00:45 +00:00
perf	intel: Move i915_drm.h specific code from common/intel_gem.h to common/i915/intel_gem.h	2023-07-28 15:36:52 +00:00
tools	intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c	2023-09-06 01:39:53 +00:00
vulkan	intel/ds: track acceleration RT commands	2023-10-06 11:10:12 +00:00
vulkan_hasvk	hasvk: Use the common GetPhysicalDeviceFeatures2 implementation	2023-09-27 23:02:29 +00:00
meson.build	intel: Only build perf if drivers or tools are enabled	2023-08-31 21:53:19 +00:00