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split ANV_PIPE_RENDER_TARGET_BUFFER_WRITES into separate CS_STALL,
RT_FLUSH & TILE_FLUSH flags in order to have finer control over cache
coherency.
Tigerlake CS has it's own cache fetching directly from the memory controller,
so we need to do a tile flush to ensure the query data is visible.
This fixes test_resolve_non_issued_query_data in vkd3d on TGL.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Fixes:
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| .. | ||
| blorp | ||
| ci | ||
| common | ||
| compiler | ||
| dev | ||
| ds | ||
| genxml | ||
| isl | ||
| nullhw-layer | ||
| perf | ||
| tools | ||
| vulkan | ||
| vulkan_hasvk | ||
| meson.build | ||