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b8889f5eaa
Mesa now has a statistics framework. This adds support for emitting additional statistics about PowerVR shaders for the Rogue architecture. Add support for emitting the following statistics: Code size, scratch size, spill count, temp count, loop count, number of inst groups, number of main inst groups, number of bitwise inst groups and number of control inst groups. Add support for new PCO_DEBUG_PRINT option "stats" to emit shader stats. Signed-off-by: Duncan Brawley <duncan.brawley@imgtec.com> Reviewed-by: Simon Perretta <simon.perretta@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39523>
204 lines
13 KiB
XML
204 lines
13 KiB
XML
<shaderdb>
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<isa name="Adreno">
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<stat name="Max Waves Per Core" display="MaxWaves" more="better" type="u16">Maximum number of simultaneous waves per core.</stat>
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<stat name="Instruction Count" display="Inst">Total number of IR3 instructions in the final generated shader executable.</stat>
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<stat name="Code size">Total number of dwords in the final generated shader executable.</stat>
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<stat name="NOPs Count" display="NOPs">Number of NOP instructions in the final generated shader executable.</stat>
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<stat name="MOV Count" display="MOV">Number of MOV instructions in the final generated shader executable.</stat>
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<stat name="COV Count" display="COV">Number of COV instructions in the final generated shader executable.</stat>
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<stat name="Registers used" display="Full" type="u16">Number of registers used in the final generated shader executable.</stat>
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<stat name="Half-registers used" display="Half" type="u16">Number of half-registers used in the final generated shader executable.</stat>
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<stat name="Last interpolation instruction" display="Last-baryf">The instruction where varying storage in Local Memory is released</stat>
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<stat name="Last helper instruction" display="Last-helper">The instruction where helper invocations are killed</stat>
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<stat name="Instructions with SS sync bit" display="(ss)">SS bit is set for instructions which depend on a result of long instructions to prevent RAW hazard.</stat>
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<stat name="Instructions with SY sync bit" display="(sy)">SY bit is set for instructions which depend on a result of loads from global memory to prevent RAW hazard.</stat>
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<stat name="Estimated cycles stalled on SS" display="(ss)-stall">A better metric to estimate the impact of SS syncs.</stat>
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<stat name="Estimated cycles stalled on SY" display="(sy)-stall">A better metric to estimate the impact of SY syncs.</stat>
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<stat name="cat# instructions" display="cat#" count="8">Number of cat# instructions.</stat>
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<stat name="Loops">Number of hardware loops</stat>
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<stat name="STP Count" display="STPs">Number of STore Private instructions in the final generated shader executable.</stat>
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<stat name="LDP Count" display="LDPs">Number of LoaD Private instructions in the final generated shader executable.</stat>
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<stat name="Preamble Instruction Count" display="Preamble inst">Total number of IR3 instructions in the preamble.</stat>
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<stat name="Early preamble" display="Early-preamble" type="bool">Whether the preamble will be executed early.</stat>
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<stat name="Const file size" display="Constlen">Size of the const file in vec4</stat>
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</isa>
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<isa name="AGX2">
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<stat name="Instructions" display="Instrs">Instruction count</stat>
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<stat name="ALU">Estimated ALU cycle count</stat>
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<stat name="FSCIB">Estimated F16/F32/SCIB cycle count</stat>
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<stat name="IC">Estimated IC cycle count</stat>
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<stat name="Code size">Binary size in bytes</stat>
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<stat name="GPRs" type="u16">Number of 16-bit GPRs</stat>
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<stat name="Uniforms" type="u16">Number of 16-bit uniform registers</stat>
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<stat name="Scratch">Scratch size per thread in bytes</stat>
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<stat name="Threads" more="better" type="u16">Maximum number of threads in flight on a compute unit</stat>
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<stat name="Loops">Number of hardware loops</stat>
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<stat name="Spills">Number of spill (stack store) instructions</stat>
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<stat name="Fills">Number of fill (stack load) instructions</stat>
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<stat name="Preamble instructions" display="Preamble inst">Preamble instruction count</stat>
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</isa>
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<family name="Pan">
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<isa name="Midgard">
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<stat name="Instructions" display="Inst">Instruction count</stat>
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<stat name="Bundles">Instruction bundles</stat>
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<stat name="Registers" type="u16">Register usage in vec4s</stat>
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<stat name="Threads" more="better" type="u16">Maximum number of threads in flight on a compute unit</stat>
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<stat name="Quadwords">Binary size in quadwords</stat>
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<stat name="Loops">Number of hardware loops</stat>
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<stat name="Spills">Number of spill instructions</stat>
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<stat name="Fills">Number of fill instructions</stat>
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</isa>
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<isa name="Bifrost">
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<stat name="Instructions" display="Instrs">Instruction count</stat>
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<stat name="Tuples">Tuple count</stat>
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<stat name="Clauses">Clause count</stat>
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<stat name="Cycles" type="float">Estimated normalized cycles</stat>
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<stat name="Arithmetic" display="Arith" type="float">Estimated normalized arithmetic cycles</stat>
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<stat name="Texture" display="T" type="float">Estimated normalized Texture cycles</stat>
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<stat name="Load/store" display="LDST" type="float">Estimated normalized Load/Store cycles</stat>
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<stat name="Varying" display="V" type="float">Estimated normalized Varying cycles</stat>
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<stat name="Preloads" type="u16">Preload count</stat>
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<stat name="Threads" more="better" type="u16">Maximum number of threads in flight on a compute unit</stat>
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<stat name="Code size">Binary size in bytes</stat>
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<stat name="Loops">Number of hardware loops</stat>
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<stat name="Spills">Number of spill instructions</stat>
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<stat name="Fills">Number of fill instructions</stat>
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<stat name="Spill cost">Cost of spill and fill instructions</stat>
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<stat name="Registers used">Number of registers used</stat>
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<stat name="Uniforms used">Uniform registers used</stat>
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</isa>
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<isa name="Valhall">
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<stat name="Instructions" display="Instrs">Instruction count</stat>
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<stat name="Cycles" type="float">Estimated normalized cycles</stat>
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<stat name="FMA" type="float">Estimated normalized FMA (Fused Multiply-Add) cycles</stat>
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<stat name="CVT" type="float">Estimated normalized CVT (ConVerT) cycles</stat>
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<stat name="SFU" type="float">Estimated normalized SFU (Special Function Unit) cycles</stat>
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<stat name="Varying" display="V" type="float">Estimated normalized Varying cycles</stat>
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<stat name="Texture" display="T" type="float">Estimated normalized Texture cycles</stat>
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<stat name="Load/store" display="LS" type="float">Estimated normalized Load/Store cycles</stat>
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<stat name="Code size">Binary size in bytes</stat>
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<stat name="Threads" more="better" type="u16">Maximum number of threads in flight on a compute unit</stat>
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<stat name="Loops">Number of hardware loops</stat>
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<stat name="Spills">Number of spill instructions</stat>
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<stat name="Fills">Number of fill instructions</stat>
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<stat name="Spill cost">Cost of spill and fill instructions</stat>
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<stat name="Registers used">Number of registers used</stat>
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<stat name="Uniforms used">Uniform registers used</stat>
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</isa>
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</family>
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<isa name="VideoCore VI">
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<stat name="Instruction Count" display="Instrs">Number of QPU instructions</stat>
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<stat name="Thread Count" more="better">Number of QPU threads dispatched</stat>
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<stat name="Spill Size">Size of the spill buffer in bytes</stat>
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<stat name="TMU Spills" display="Spills">Number of times a register was spilled to memory</stat>
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<stat name="TMU Fills" display="Fills">Number of times a register was filled from memory</stat>
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<stat name="QPU Read Stalls" display="Read Stalls">Number of cycles the QPU stalls for a register read dependency</stat>
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</isa>
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<isa name="AMD">
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<stat name="Driver pipeline hash" display="DriverHash" hash="true" type="u64">Driver pipeline hash used by RGP</stat>
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<stat name="SGPRs">Number of SGPR registers allocated per subgroup</stat>
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<stat name="VGPRs">Number of VGPR registers allocated per subgroup</stat>
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<stat name="Spilled SGPRs" display="SpillSGPRs">Number of SGPR registers spilled per subgroup</stat>
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<stat name="Spilled VGPRs" display="SpillVGPRs">Number of VGPR registers spilled per subgroup</stat>
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<stat name="Code size" display="CodeSize">Code size in bytes</stat>
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<stat name="LDS size" display="LDS">LDS size in bytes per workgroup</stat>
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<stat name="Scratch size" display="Scratch">Private memory in bytes per subgroup</stat>
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<stat name="Subgroups per SIMD" display="MaxWaves" more="better">The maximum number of subgroups in flight on a SIMD unit</stat>
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<stat name="Combined inputs" display="Inputs">Number of input slots reserved for the shader (including merged stages)</stat>
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<stat name="Combined outputs" display="Outputs">Number of output slots reserved for the shader (including merged stages)</stat>
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<stat name="Hash" hash="true">CRC32 hash of code and constant data</stat>
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<stat name="Instructions" display="Instrs">Instruction count</stat>
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<stat name="Copies">Copy instructions created for pseudo-instructions</stat>
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<stat name="Branches">Branch instructions</stat>
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<stat name="Latency">Issue cycles plus stall cycles</stat>
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<stat name="Inverse Throughput" display="InvThroughput">Estimated busy cycles to execute one wave</stat>
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<stat name="VMEM Clause" display="VClause">Number of VMEM clauses (includes 1-sized clauses)</stat>
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<stat name="SMEM Clause" display="SClause">Number of SMEM clauses (includes 1-sized clauses)</stat>
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<stat name="Pre-Sched SGPRs" display="PreSGPRs">SGPR usage before scheduling</stat>
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<stat name="Pre-Sched VGPRs" display="PreVGPRs">VGPR usage before scheduling</stat>
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<stat name="VALU">Number of VALU instructions</stat>
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<stat name="SALU">Number of SALU instructions</stat>
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<stat name="VMEM">Number of VMEM instructions</stat>
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<stat name="SMEM">Number of SMEM instructions</stat>
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<stat name="VOPD" more="better">Number of VOPD instructions</stat>
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</isa>
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<family name="Intel">
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<isa name="GenISA">
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<stat name="Dispatch width" hidden="true">0 for vec4</stat>
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<stat name="Max polygons" hidden="true"/>
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<stat name="Instruction Count" display="Instrs">
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Number of GEN instructions in the final generated shader executable.
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</stat>
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<stat name="SEND Count" display="Send messages">
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Number of instructions in the final generated shader executable
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which access external units such as the constant cache or the sampler.
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</stat>
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<stat name="Loop Count" display="Loop count">
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Number of loops (not unrolled) in the final generated shader
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executable.
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</stat>
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<stat name="Cycle Count" display="Cycle count">
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Estimate of the number of EU cycles required to execute the final
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generated executable. This is an estimate only and may vary greatly
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from actual run-time performance.
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</stat>
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<stat name="Spill Count" display="Spill count">
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Number of scratch spill operations. This gives a rough estimate of
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the cost incurred due to spilling temporary values to memory. If
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this is non-zero, you may want to adjust your shader to reduce
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register pressure.
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</stat>
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<stat name="Fill Count" display="Fill count">
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Number of scratch fill operations. This gives a rough estimate of
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the cost incurred due to spilling temporary values to memory. If
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this is non-zero, you may want to adjust your shader to reduce
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register pressure.
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</stat>
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<stat name="Scratch Memory Size">
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Number of bytes of scratch memory required by the generated shader
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executable. If this is non-zero, you may want to adjust your shader
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to reduce register pressure.
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</stat>
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<stat name="GRF registers">
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Number of GRF registers required by the shader.
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</stat>
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<stat name="Max dispatch width" more="better">
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Largest SIMD dispatch width.
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</stat>
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<stat name="Max live registers">
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Maximum number of registers used across the entire shader.
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</stat>
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<stat name="Workgroup Memory Size">
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Number of bytes of workgroup shared memory used by this shader
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including any padding.
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</stat>
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<stat name="Non SSA regs after NIR">
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Non SSA regs after NIR translation to BRW.
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</stat>
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<stat name="Source hash" hash="true">
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Hash generated from shader source.
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</stat>
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</isa>
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</family>
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<family name="PVR">
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<isa name="Rogue">
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<stat name="Code size">Binary size in bytes</stat>
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<stat name="Scratch size">Scratch size per instance in bytes</stat>
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<stat name="Spill count">Number of spilled registers per instance</stat>
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<stat name="Temp count">Number of allocated temp registers</stat>
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<stat name="Loop count">Number of not unrolled loops in the shader</stat>
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<stat name="Inst group count">Total number of instruction groups</stat>
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<stat name="Main inst group count">Number of main instruction groups</stat>
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<stat name="Bitwise inst group count">Number of bitwise instruction groups</stat>
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<stat name="Control inst group count">Number of control instruction groups</stat>
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</isa>
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</family>
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</shaderdb>
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