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f4c05f319e
Fixes: 32c5d6d1dc ("iris: Add an alignment parameter to iris_bo_alloc()")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15811>
104 lines
4.1 KiB
C
104 lines
4.1 KiB
C
/*
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* Copyright © 2019 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "iris_perf.h"
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#include "iris_context.h"
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static void *
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iris_oa_bo_alloc(void *bufmgr, const char *name, uint64_t size)
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{
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return iris_bo_alloc(bufmgr, name, size, 64, IRIS_MEMZONE_OTHER, BO_ALLOC_SMEM);
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}
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static void
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iris_perf_emit_stall_at_pixel_scoreboard(struct iris_context *ice)
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{
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iris_emit_end_of_pipe_sync(&ice->batches[IRIS_BATCH_RENDER],
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"OA metrics",
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PIPE_CONTROL_STALL_AT_SCOREBOARD);
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}
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static void
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iris_perf_emit_mi_report_perf_count(void *c,
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void *bo,
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uint32_t offset_in_bytes,
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uint32_t report_id)
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{
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struct iris_context *ice = c;
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struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
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batch->screen->vtbl.emit_mi_report_perf_count(batch, bo, offset_in_bytes, report_id);
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}
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static void
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iris_perf_batchbuffer_flush(void *c, const char *file, int line)
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{
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struct iris_context *ice = c;
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_iris_batch_flush(&ice->batches[IRIS_BATCH_RENDER], __FILE__, __LINE__);
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}
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static void
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iris_perf_store_register_mem(void *ctx, void *bo,
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uint32_t reg, uint32_t reg_size,
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uint32_t offset)
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{
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struct iris_context *ice = ctx;
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struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
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if (reg_size == 8) {
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batch->screen->vtbl.store_register_mem64(batch, reg, bo, offset, false);
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} else {
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assert(reg_size == 4);
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batch->screen->vtbl.store_register_mem32(batch, reg, bo, offset, false);
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}
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}
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typedef void (*bo_unreference_t)(void *);
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typedef void *(*bo_map_t)(void *, void *, unsigned flags);
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typedef void (*bo_unmap_t)(void *);
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typedef void (*emit_mi_report_t)(void *, void *, uint32_t, uint32_t);
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typedef void (*emit_mi_flush_t)(void *);
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typedef void (*store_register_mem_t)(void *ctx, void *bo,
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uint32_t reg, uint32_t reg_size,
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uint32_t offset);
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typedef bool (*batch_references_t)(void *batch, void *bo);
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typedef void (*bo_wait_rendering_t)(void *bo);
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typedef int (*bo_busy_t)(void *bo);
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void
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iris_perf_init_vtbl(struct intel_perf_config *perf_cfg)
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{
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perf_cfg->vtbl.bo_alloc = iris_oa_bo_alloc;
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perf_cfg->vtbl.bo_unreference = (bo_unreference_t)iris_bo_unreference;
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perf_cfg->vtbl.bo_map = (bo_map_t)iris_bo_map;
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perf_cfg->vtbl.bo_unmap = (bo_unmap_t)iris_bo_unmap;
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perf_cfg->vtbl.emit_stall_at_pixel_scoreboard =
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(emit_mi_flush_t)iris_perf_emit_stall_at_pixel_scoreboard;
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perf_cfg->vtbl.emit_mi_report_perf_count =
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(emit_mi_report_t)iris_perf_emit_mi_report_perf_count;
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perf_cfg->vtbl.batchbuffer_flush = iris_perf_batchbuffer_flush;
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perf_cfg->vtbl.store_register_mem =
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(store_register_mem_t) iris_perf_store_register_mem;
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perf_cfg->vtbl.batch_references = (batch_references_t)iris_batch_references;
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perf_cfg->vtbl.bo_wait_rendering =
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(bo_wait_rendering_t)iris_bo_wait_rendering;
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perf_cfg->vtbl.bo_busy = (bo_busy_t)iris_bo_busy;
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}
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