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b5e7907f30
The llvm TGSI backend uses pointers in registers and does things like: LOAD TEMP[0].y, MEMORY[0], TEMP[0] Expecting the data at address TEMP[0].x to get loaded to TEMP[0].y. But this will cause the data at TEMP[0].x + 4 to be loaded instead. This commit adds support for a swizzle suffix for the 1st source operand, which allows using: LOAD TEMP[0].y, MEMORY[0].xxxx, TEMP[0] And actually getting the desired behavior Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> |
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| .. | ||
| cso | ||
| drivers | ||
| exts | ||
| conf.py | ||
| context.rst | ||
| cso.rst | ||
| debugging.rst | ||
| distro.rst | ||
| drivers.rst | ||
| format.rst | ||
| glossary.rst | ||
| index.rst | ||
| intro.rst | ||
| pipeline.txt | ||
| resources.rst | ||
| screen.rst | ||
| tgsi.rst | ||